Hermetic package for high CTE mismatch

Patent metadata

Field	Value
Publication number	US-12266582-B2
Application number	US-202117394083-A
Country	US
Kind code	B2
Filing date	Aug 4, 2021
Priority date	Aug 4, 2020
Publication date	Apr 1, 2025
Grant date	Apr 1, 2025

Abstract

The present disclosure relates to a hermetic package capable of handling a high coefficient of thermal expansion (CTE) mismatch configuration. The disclosed hermetic package includes a metal base and multiple segments that are discrete from each other. Herein, a gap exists between every two adjacent ceramic wall segments and is sealed with a connecting material. The ceramic wall segments with the connecting material form a ring wall, where the gap between every two adjacent ceramic wall segments is located at a corner of the ring wall. The metal base is either surrounded by the ring wall or underneath the ring wall.

First claim

What is claimed is:

1. A package comprising:
a metal base having a top surface; and
multiple ceramic wall segments discrete from each other and having no overlap in a horizontal plane, wherein:
a gap exists between every two adjacent ceramic wall segments and is sealed with a connecting material, wherein the ceramic wall segments and the connecting material are formed of different materials;
each of the ceramic wall segments and the connecting material form a ring wall, wherein the gap between every two adjacent ceramic wall segments is located at a corner of the ring wall;
the metal base has a coefficient of thermal expansion (CTE)>11 μm/m·K, and each ceramic wall segment has a CTE<9 μm/m·K; and
the metal base is surrounded by the ring wall, wherein each side surface of the metal base is fully covered by the ring wall, and at least a portion of the top surface of the metal base is exposed through the ring wall.

2. The package of claim 1 wherein the gap that exists between every two adjacent ceramic wall segments is less than 50 thousandth of an inch.

3. The package of claim 1 wherein:
the metal base is formed of copper, copper molybdenum, or copper tungsten; and
each ceramic wall segment is formed of alumina.

4. The package of claim 1 wherein the number of the ceramic wall segments is four, and every two adjacent ceramic wall segments are orthogonal.

5. The package of claim 4 wherein the four ceramic wall segments are identical, and the ring wall is a square ring wall.

6. The package of claim 4 wherein:
each ceramic wall segment has two end sides, and a surface of each end side is metalized; and
each gap is formed between the metalized surfaces of the end sides of every two adjacent ceramic wall segments.

7. The package of claim 6 wherein:
each ceramic wall segment includes a top region and a bottom region underneath the top region;
the bottom region is smaller than the top region, wherein inside portions of the top region extend beyond the bottom region, such that each ceramic wall segment has a castellation internal side;
recess surfaces of the castellation internal side are metalized; and
the metal base is surrounded by the four ceramic wall segments and embedded among the castellation internal side of each ceramic wall segment, such that a portion of the top region of each ceramic wall segment resides over the top surface of the metal base, wherein each side surface of the metal base and a peripheral portion of the top surface of the metal base are connected to the metalized recess surfaces of the castellation internal side of each ceramic wall segment via the connecting material.

8. The package of claim 7 further comprising a ring structure attached to a peripheral portion of a top surface of the top region of each ceramic wall segment via the connecting material, such that the top surface of the top region of each ceramic wall segment is partially exposed through the ring structure.

9. The package of claim 8 wherein:
the ring structure is formed of a copper alloy or an iron alloy; and
the peripheral portion of the top surface of the top region of each ceramic wall segment is metalized.

10. The package of claim 9 further comprising a lid placed over the ring structure, wherein the lid is formed of a copper alloy or an iron alloy, and the ring structure is configured to provide a consistent sealing surface to the lid.

11. The package of claim 10 wherein the metal base, the ring wall, the ring structure, the lid, and the connecting material form a hermetic cavity, which is capable of accommodating at least one semiconductor die, wherein the at least one semiconductor die is mounted on the at least exposed portion of the top surface of the metal base and located within the hermetic cavity.

12. The package of claim 7 wherein:
the top region has a trapezoidal shape in a horizontal plane, and the bottom region has a trapezoidal shape in a horizontal plane; and
each ceramic wall segment has an external side with a flat surface, and the surface of each end side of each ceramic wall segment is an inclined surface.

13. The package of claim 6 wherein:
each ceramic wall segment includes a top region and a bottom region underneath the top region;
the bottom region is larger than the top region, wherein inside portions of the bottom region extend beyond the top region, such that each ceramic wall segment has a castellation internal side;
an inside surface of the bottom region of each ceramic wall segment is metalized; and
the metal base is surrounded by the four ceramic wall segments and embedded among the bottom region of each ceramic wall segment, wherein:
the top region of each ceramic wall segment does not extend over any portion of the top surface of the metal base, and the top surface of the metal base is fully exposed through the four ceramic wall segments; and
each side surface of the metal base is connected to the metalized inside surface of the bottom region of a corresponding ceramic wall segment via the connecting material.

14. The package of claim 13 further comprising a lid formed of a ceramic material, wherein the lid is placed over the top region of each ceramic wall segment.

15. The package of claim 14 wherein:
each ceramic wall segment is formed of alumina, wherein a top surface of the top region of each ceramic wall segment is metalized;
the lid is formed of alumina, wherein a peripheral portion of a bottom surface of the lid is metalized; and
the metalized peripheral portion of the bottom surface of the lid is connected to the metalized top surface of the top region of each ceramic wall segment via the connecting material.

16. The package of claim 14 wherein the metal base, the ring wall, the lid, and the connecting material form a hermetic cavity, which is capable of accommodating at least one semiconductor die, wherein the at least one semiconductor die is mounted on the exposed top surface of the metal base and located within the hermetic cavity.

17. The package of claim 13 wherein:
the top region has a trapezoidal shape in a horizontal plane, and the bottom region has a trapezoidal shape in a horizontal plane; and
each ceramic wall segment has an external side with a flat surface, and the surface of each end side of each ceramic wall segment is an inclined surface.

18. The package of claim 6 wherein the surface of each end of each ceramic wall segment is metalized by a metal combination, which includes Titanium Tungsten (TiW), nickel (Ni) over TiW, and gold (Au) over Ni.

19. The package of claim 1 wherein the connecting material is a solder or a brazing alloy.

20. The package of claim 1 wherein:
the metal base is formed of a layered stack of copper and tungsten or a layered stack of copper and moly; and
each ceramic wall segment is formed of alumina.

21. The package of claim 1 wherein each side surface of the metal base is connected to the ring wall through a metal combination, which includes TiW, Ni over TiW, and Au over Ni.

Assignees

• Qorvo Us Inc

Inventors

• Murdock Dylan

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W76/17

  characterised by their materials · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title