Multiple process semiconductor processing system

Patent metadata

Field	Value
Publication number	US-12266550-B2
Application number	US-202016932795-A
Country	US
Kind code	B2
Filing date	Jul 19, 2020
Priority date	Jul 19, 2020
Publication date	Apr 1, 2025
Grant date	Apr 1, 2025

Abstract

Exemplary substrate processing systems may include a plurality of processing regions. The systems may include a transfer region housing defining a transfer region fluidly coupled with the plurality of processing regions. The systems may include a plurality of substrate supports. Each substrate support of the plurality of substrate supports may be vertically translatable between the transfer region and an associated processing region of the plurality of processing regions. The systems may include a transfer apparatus including a rotatable shaft extending through the transfer region housing. The transfer apparatus may also include an end effector coupled with the rotatable shaft. The systems may include an exhaust foreline including a plurality of foreline tails. Each foreline tail of the plurality of foreline tails may be fluidly coupled with a separate processing region of the plurality of processing regions. The systems may include a plurality of throttle valves.

First claim

The invention claimed is:

1. A method of semiconductor processing comprising:
delivering one or more processing precursors through a plurality of faceplates of a substrate processing system, each faceplate of the plurality of faceplates fluidly accessing a processing region of a plurality of processing regions, wherein each processing region of the plurality of processing regions is at least partially defined by a faceplate of the plurality of faceplates and comprise a substrate support of a plurality of substrate supports;
adjusting a flow rate of the one or more processing precursors to form a pressure differential between two processing regions of the plurality of processing regions;
delivering a purge gas into a plurality of transfer regions of the substrate processing system through a plurality of purge channels extending through a transfer region housing defining the plurality of transfer regions, wherein the plurality of transfer regions are fluidly coupled with a processing region of the plurality of processing regions and is disposed below each substrate support of the plurality of substrate supports when the plurality of substrate supports are positioned within the plurality of processing regions;
adjusting a flow rate of the purge gas into one or more transfer regions of the plurality of transfer regions through a choking liner extending from each substrate support of the plurality of substrate supports towards the plurality of transfer regions of the substrate processing system, corresponding to a pressure of one or more processing regions of the plurality of processing regions; and
exhausting the one or more processing precursors and the purge gas through a pumping liner seated below each faceplate of the plurality of faceplates.

2. The method of semiconductor processing of claim 1 , wherein the pressure differential is greater than or about 10 Torr between the two processing regions of the plurality of processing regions.

3. The method of semiconductor processing of claim 1 , wherein the substrate processing system comprises a transfer apparatus positioned in the plurality of transfer region, the transfer apparatus comprising:
a rotatable shaft extending through the transfer region housing, and
an end effector coupled with the rotatable shaft, wherein the end effector includes a central hub defining a central aperture fluidly coupled with a purge source, and wherein the end effector further includes a plurality of arms having a number of arms equal to a number of substrate supports of the plurality of substrate supports.

4. The method of semiconductor processing of claim 1 , wherein the delivering comprises:
delivering a first precursor to a first processing region of the two processing regions of the plurality of processing regions; and
delivering a second precursor to a second processing region of the two processing regions of the plurality of processing regions.

5. The method of semiconductor processing of claim 4 , wherein the first precursor or the second precursor is a deposition precursor.

6. The method of semiconductor processing of claim 1 , wherein each choking liner defines a plurality of apertures providing fluid communication between the plurality of processing regions and the plurality of transfer regions when the substrate support is in a raised position for processing.

7. The method of semiconductor processing of claim 6 , wherein the purge gas is delivered from the plurality of transfer regions through the plurality of apertures defined in the choking liner.

8. The method of semiconductor processing of claim 1 , wherein the substrate processing system further comprises:
a system foreline including a plurality of foreline tails, each foreline tail of the plurality of foreline tails fluidly coupling with a separate processing region of the plurality of processing regions.

9. The method of semiconductor processing of claim 8 , wherein the substrate processing system further comprises:
a plurality of throttle valves, wherein a throttle valve of the plurality of throttle valves is incorporated in each foreline tail of the plurality of foreline tails.

10. The method of semiconductor processing of claim 9 , further comprising:
modulating a first throttle valve of the plurality of throttle valves separately from a second throttle valve of the plurality of throttle valves to maintain the pressure differential between the two processing regions of the plurality of processing regions.

11. The method of semiconductor processing of claim 1 , wherein the one or more processing precursors are limited or prevented from flowing into the plurality of transfer regions of the substrate processing system by the purge gas.

12. The method of semiconductor processing of claim 1 , wherein the plurality of transfer regions extends below each processing region.

Assignees

• Applied Materials Inc

Inventors

• Pathak Nitin
• Prabhakar Vinay K
• Ramamurthi Badri N
• Kalsekar Viren
• Rocha-Alvarez Juan Carlos

Classifications

• H10P72/3308

  Vertical transfer of a single workpiece · CPC title

• H10P72/0454

  surrounding a central transfer chamber · CPC title

• H10P72/0402

  Apparatus for fluid treatment (H10P72/0441, H10P72/0448 take precedence) · CPC title

• H10P72/0464 Primary

  characterised by the construction of the transfer chamber · CPC title

• H10P72/7621

  characterised by supporting two or more semiconductor substrates · CPC title