Semiconductor base plate and semiconductor device

Patent metadata

Field	Value
Publication number	US-12256536-B2
Application number	US-202217662891-A
Country	US
Kind code	B2
Filing date	May 11, 2022
Priority date	Sep 1, 2021
Publication date	Mar 18, 2025
Grant date	Mar 18, 2025

Abstract

Embodiments of the present disclosure disclose a semiconductor base plate and a semiconductor device. An array region includes a primary memory cell. A peripheral region includes an antifuse memory cell. The antifuse memory cell and the primary memory cell are formed by a same process.

First claim

The invention claimed is:

1. A semiconductor base plate, comprising:
a semiconductor substrate, comprising an array region and a peripheral region, wherein
the array region comprises a primary memory cell;
the peripheral region comprises an antifuse memory cell and secondary memory capacitors, one of the secondary memory capacitors is electrically connected to the antifuse memory cell;
the peripheral region further comprises a repair control circuit, the repair control circuit is connected to the antifuse memory cell, and the repair control circuit is connected to the secondary memory capacitor by using the antifuse memory cell, and when it is determined that a primary memory cell in the array region is damaged, the repair control circuit is configured to control a corresponding antifuse memory cell to operate, to replace the damaged primary memory cell with the secondary memory capacitor connected electrically; and
the antifuse memory cell and the primary memory cell formed by a same process.

2. The semiconductor base plate according to claim 1 , wherein
film layers having a same function in functional members in the antifuse memory cell and in the primary memory cell are formed by a one-time patterning process.

3. The semiconductor base plate according to claim 2 , wherein
the primary memory cell comprises a primary control transistor; and the antifuse memory cell comprises an antifuse control transistor; and
film layers having a same function in the primary control transistor and in the antifuse control transistor are formed by a one-time patterning process.

4. The semiconductor base plate according to claim 3 , wherein
a gate of the primary control transistor and a gate of the antifuse control transistor have a same pattern by using a same mask;
an active region of the primary control transistor and an active region of the antifuse control transistor have a same pattern by using a same mask;
a source of the primary control transistor and a source of the antifuse control transistor have a same pattern by using a same mask; and
a drain of the primary control transistor and a drain of the antifuse control transistor have a same pattern by using a same mask.

5. The semiconductor base plate according to claim 3 , wherein
the primary memory cell further comprises a primary memory capacitor; and the antifuse memory cell further comprises an antifuse memory capacitor;
a first isolation layer is provided between a layer in which the primary memory capacitor and the antifuse memory capacitor are located and a layer in which the primary control transistor and the antifuse control transistor are located; the first isolation layer is provided with a primary through hole and a secondary through hole; and the primary memory capacitor is electrically connected to the primary control transistor through the primary through hole, and the antifuse memory capacitor is electrically connected to the antifuse control transistor through the secondary through hole; and
film layers having a same function in the primary memory capacitor and in the antifuse memory capacitor are formed by using a same mask.

6. The semiconductor base plate according to claim 5 , wherein
the primary memory capacitor comprises a primary first electrode plate and a primary second electrode plate; and the primary first electrode plate is electrically connected to the primary control transistor through the primary through hole;
the antifuse memory capacitor comprises a secondary first electrode plate and a secondary second electrode plate; and the secondary first electrode plate is electrically connected to the antifuse control transistor through the secondary through hole; and
the primary first electrode plate and the secondary first electrode plate have a same pattern by using a same mask.

7. The semiconductor base plate according to claim 6 , wherein
the primary memory capacitor and the antifuse memory capacitor are columnar.

8. The semiconductor base plate according to claim 6 , wherein
the primary through hole and the secondary through hole have a same pattern by using a same mask.

9. The semiconductor base plate according to claim 6 , further comprising:
a primary contact pad located in the primary through hole and a secondary contact pad located in the secondary through hole;
the primary first electrode plate is electrically connected to the primary control transistor by using the primary contact pad; and
the secondary first electrode plate is electrically connected to the antifuse control transistor by using the secondary contact pad.

10. The semiconductor base plate according to claim 9 , wherein
the primary contact pad and the secondary contact pad are formed by using a same preparation process.

11. The semiconductor base plate according to claim 5 , wherein
the array region comprises a plurality of primary bit lines, and the peripheral region comprises a plurality of secondary bit lines; and
the plurality of primary bit lines and the plurality of secondary bit lines are formed by using a same preparation process.

12. The semiconductor base plate according to claim 11 , wherein
the plurality of primary bit lines and the plurality of secondary bit lines have a same pattern by using a same mask.

13. The semiconductor base plate according to claim 5 , wherein
the secondary memory capacitor and a primary memory capacitor of the primary memory cell are of a same structure.

14. A semiconductor device, comprising
the semiconductor base plate according to claim 1 .

Assignees

• Changxin Memory Tech Inc

Inventors

• Long Qiang

Classifications

• H10B20/25

  One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links · CPC title

• H10B20/20 Primary

  Programmable ROM [PROM] devices comprising field-effect components (H10B20/10 takes precedence) · CPC title