Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2016190145-A1
Application number	US-201514972260-A
Country	US
Kind code	A1
Filing date	Dec 17, 2015
Priority date	Dec 25, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

A semiconductor device includes an SOI substrate and an anti-fuse element formed on the SOI substrate. The SOI substrate has a p type well region formed on a main surface side of a support substrate and an SOI layer formed on the p type well region via a BOX layer. The anti-fuse element has a gate electrode formed on the SOI layer via agate insulating film. The anti-fuse element constitutes a storage element, and a first potential is applied to the gate electrode and a second potential of the same polarity as the first potential is applied to the p type well region in a write operation of the storage element.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a semiconductor substrate; and an anti-fuse element formed on the semiconductor substrate, wherein the semiconductor substrate includes: a base member; a first semiconductor region of a first conductivity type formed on a main surface side of the base member; a first insulating layer formed on the first semiconductor region; and a first semiconductor layer formed on the first insulating layer, the anti-fuse element includes: a first gate electrode formed on the first semiconductor layer via a first gate insulating film; and a second semiconductor region of a second conductivity type opposite to the first conductivity type formed in a part of the first semiconductor layer located on a first side with respect to the first gate electrode, the anti-fuse element constitutes a storage element, and a first potential is applied to the first gate electrode and a second potential having the same polarity as the first potential is applied to the first semiconductor region in a write operation of the storage element.

2 . The semiconductor device according to claim 1 ,
wherein a potential of the first semiconductor region is a ground potential in a read operation of the storage element.

3 . The semiconductor device according to claim 1 ,
wherein the first conductivity type is a p type, the second conductivity type is an n type, the first gate electrode is made of an n type first semiconductor film, and the first potential and the second potential are both positive potentials.

4 . The semiconductor device according to claim 1 ,
wherein the first conductivity type is a p type, the second conductivity type is an n type, the first gate electrode is made of a p type second semiconductor film, and the first potential and the second potential are both negative potentials.

5 . The semiconductor device according to claim 1 , further comprising:
a first field effect transistor formed on the semiconductor substrate, wherein the first conductivity type is a p type, the second conductivity type is an n type, the first semiconductor region is formed in a first region on the main surface side of the base member, the first gate electrode is made of a third semiconductor film to which an n type first impurity is introduced, the semiconductor substrate includes: a p type third semiconductor region formed in a second region on the main surface side of the base member; a second insulating layer formed on the third semiconductor region; and a second semiconductor layer formed on the second insulating layer, the first field effect transistor includes: a second gate electrode formed on the second semiconductor layer via a second gate insulating film; and an n type fourth semiconductor region formed in a part of the second semiconductor layer located on a second side with respect to the second gate electrode, the second gate electrode is made of a fourth semiconductor film to which an n type second impurity is introduced, a concentration of the first impurity in the first gate electrode is lower than a concentration of the second impurity in the second gate electrode, and the first potential and the second potential are both negative potentials.

6 . The semiconductor device according to claim 1 ,
wherein the first conductivity type is a p type, the second conductivity type is an n type, the first gate electrode is made of a fifth semiconductor film to which an n type third impurity is introduced, a concentration of the third impurity in a part of the first gate electrode, which is in contact with the first gate insulating film, is lower than a concentration of the third impurity in an upper layer part of the first gate electrode, and the first potential and the second potential are both negative potentials.

7 . The semiconductor device according to claim 1 , further comprising:
a second field effect transistor formed on the semiconductor substrate, wherein the first conductivity type is a p type, the second conductivity type is an n type, the first semiconductor region is formed in a third region on the main surface side of the base member, the first gate electrode is made of a sixth semiconductor film to which an n type fourth impurity is introduced, the semiconductor substrate includes: a p type fifth semiconductor region formed in a fourth region on the main surface side of the base member; a third insulating layer formed on the fifth semiconductor region; and a third semiconductor layer formed on the third insulating layer, the second field effect transistor includes: a third gate electrode formed on the third semiconductor layer via a third gate insulating film; and an n type sixth semiconductor region formed in a part of the third semiconductor layer located on a third side with respect to the third gate electrode, the third gate electrode is made of a seventh semiconductor film to which an n type fifth impurity is introduced, the second semiconductor region is formed in a part of the first semiconductor layer located on the first side with respect to the first gate electrode in a first gate length direction of the first gate electrode, the sixth semiconductor region is formed in a part of the third semiconductor layer located on the third side with respect to the third gate electrode in a second gate length direction of the third gate electrode, the second semiconductor region overlaps with the part of the first gate electrode on the first side when seen in a plan view, the sixth semiconductor region overlaps with the part of the third gate electrode on the third side when seen in a plan view, and a length of the part of the second semiconductor region in the first gate length direction, which overlaps with the first gate electrode, is longer than a length of the part of the sixth semiconductor region in the second gate length direction, which overlaps with the third gate electrode.

8 . The semiconductor device according to claim 1 , further comprising:
a third field effect transistor formed on the semiconductor substrate, wherein the first semiconductor region is formed in a fifth region on the main surface side of the base member, the semiconductor substrate includes: a seventh semiconductor region of the first conductivity type formed in a sixth region on the main surface side of the base member; a fourth insulating layer formed on the seventh semiconductor region; and a fourth semiconductor layer formed on the fourth insulating layer, the third field effect transistor includes: a fourth gate electrode formed on the fourth semiconductor layer via a fourth gate insulating film; and an eighth semiconductor region of the second conductivity type formed in a part of the fourth semiconductor layer located on a fourth side with respect to the fourth gate electrode, and a third potential different from the second potential is applied to the eighth semiconductor region in the write operation of the storage element.

9 . The semiconductor device according to claim 1 , further comprising:
a fourth field effect transistor formed on the semiconductor substrate, wherein the fourth field effect transistor includes: a fifth gate electrode formed via a fifth gate insulating film on a part of the first semiconductor layer located on a side opposite to the first gate electrode with the second semiconductor region interposed therebetween; and a ninth semiconductor region of the second conductivity type formed in a part of the first semiconductor layer located on a side opposite to the second semiconductor region with the fifth gate electrode interposed therebetween, the anti-fuse element

Assignees

• Renesas Electronics Corp

Inventors

• Maekawa Keiichi
• Yoshida Shoji
• Takeuchi Takashi
• Yanagita Hiroshi

Classifications

• H10W20/491

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• G11C17/12 Primary

  using field-effect devices · CPC title

• H10D87/00

  Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate · CPC title

• H01L27/11206 Primary

  Electricity · mapped topic

• H10B20/25

  One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links · CPC title