Circuit systems and methods for reducing power supply voltage droop

Patent metadata

Field	Value
Publication number	US-12255648-B2
Application number	US-202117350577-A
Country	US
Kind code	B2
Filing date	Jun 17, 2021
Priority date	Jun 17, 2021
Publication date	Mar 18, 2025
Grant date	Mar 18, 2025

Abstract

A circuit system includes a first integrated circuit die having a first group of circuits configured to perform a first set of operations. The circuit system also includes a second integrated circuit die having a second group of circuits configured to start performing a second set of operations with a delay after the first group of circuits starts performing the first set of operations to reduce power supply voltage droop. The operations performed by the first and second groups of circuits can be interleaved with a fixed or a variable delay. Logic circuits can be partitioned into the first and the second groups of circuits based on predicted switching activity of the logic circuits. Decoupling capacitors in integrated circuit dies can be coupled together to reduce droop in a supply voltage during a high current event.

First claim

What is claimed is:

1. A circuit system comprising:
a first integrated circuit die comprising a first group of circuits configured to perform a first set of operations; and
a second integrated circuit die comprising a second group of circuits configured to start performing a second set of operations with a first delay after the first group of circuits starts performing the first set of operations to reduce power supply voltage droop, wherein logic circuits are partitioned into the first and the second groups of circuits based on predicted switching activity of the logic circuits.

2. The circuit system of claim 1 , wherein the second group of circuits is configured to start performing the second set of operations before the first group of circuits finishes performing the first set of operations to reduce the power supply voltage droop, and wherein the first delay is programmable.

3. The circuit system of claim 1 , wherein the second group of circuits is configured to start performing the second set of operations after the first group of circuits finishes performing the first set of operations to reduce the power supply voltage droop, and wherein the first delay is programmable.

4. The circuit system of claim 1 , wherein the first integrated circuit die further comprises a third group of circuits configured to perform a third set of operations with a second delay after the first group of circuits starts performing the first set of operations, wherein the second integrated circuit die further comprises a fourth group of circuits configured to perform a fourth set of operations with a third delay after the second group of circuits starts performing the second set of operations, and wherein the second group of circuits is configured to start performing the second set of operations with a fourth delay after the third group of circuits starts performing the third set of operations.

5. The circuit system of claim 4 , wherein the third group of circuits is configured to start performing the third set of operations before the first group of circuits finishes performing the first set of operations, and wherein the fourth group of circuits is configured to start performing the fourth set of operations before the second group of circuits finishes performing the second set of operations.

6. The circuit system of claim 4 , wherein the third group of circuits is configured to start performing the third set of operations after the first group of circuits finishes performing the first set of operations, and wherein the fourth group of circuits is configured to start performing the fourth set of operations after the second group of circuits finishes performing the second set of operations.

7. The circuit system of claim 4 , wherein the first and the second sets of operations are part of a first operation thread, wherein the third and the fourth sets of operations are part of a second operation thread, and wherein the circuit system is a three dimensional circuit system comprising a third integrated circuit die that is vertically stacked with and coupled to the first and the second integrated circuit dies.

8. The circuit system of claim 1 further comprising:
a third integrated circuit die comprising a third group of circuits configured to start performing a third set of operations with a second delay after the second group of circuits starts performing the second set of operations to reduce the power supply voltage droop, wherein the first, the second, and the third groups of circuits have an identical circuit structure.

9. The circuit system of claim 8 , wherein the third group of circuits is configured to start performing the third set of operations before the second group of circuits finishes performing the second set of operations to reduce the power supply voltage droop.

10. The circuit system of claim 8 , wherein the third group of circuits is configured to start performing the third set of operations after the second group of circuits finishes performing the second set of operations to reduce the power supply voltage droop.

11. A method of operating a circuit system to reduce voltage droop in a supply voltage, the method comprising:
performing a first set of operations using a first group of circuits in a first integrated circuit die;
performing a second set of operations using a second group of circuits in a second integrated circuit die with a first delay after the first group of circuits starts performing the first set of operations; and
partitioning logic circuits into the first and the second groups of circuits based on predicted switching activity of the logic circuits.

12. The method of claim 11 , wherein performing the second set of operations using the second group of circuits further comprises starting to perform the second set of operations before the first group of circuits finishes performing the first set of operations to reduce the voltage droop, and wherein the first delay is programmable.

13. The method of claim 11 , wherein performing the second set of operations using the second group of circuits further comprises starting to perform the second set of operations after the first group of circuits finishes performing the first set of operations to reduce the voltage droop, and wherein the first delay is programmable.

14. The method of claim 11 further comprising:
performing a third set of operations using a third group of circuits in the first integrated circuit die with a second delay after the first group of circuits starts performing the first set of operations; and
performing a fourth set of operations using a fourth group of circuits in the second integrated circuit die with a third delay after the second group of circuits starts performing the second set of operations,
wherein performing the second set of operations using the second group of circuits further comprises performing the second set of operations with a fourth delay after the third group of circuits starts performing the third set of operations.

15. The method of claim 14 further comprising:
partitioning the logic circuits into the first, the second, the third, and the fourth groups of circuits based on the predicted switching activity of the logic circuits.

16. The method of claim 11 further comprising:
performing a third set of operations using a third group of circuits in a third integrated circuit die with a second delay after the second group of circuits starts performing the second set of operations to reduce the voltage droop, wherein the first, the second, and the third groups of circuits have an identical circuit structure.

17. The method of claim 11 ,
wherein the first and the second sets of operations are part of an operation thread.

18. A circuit system comprising:
a first integrated circuit die comprising a first state machine circuit;
a second integrated circuit die comprising a second state machine circuit and a first decoupling capacitor; and
a third integrated circuit die comprising a third state machine circuit and a second decoupling capacitor, wherein the first state machine circuit instructs the second and the third state machine circuits to cause the first decoupling capacitor to be coupled to the second decoupling capacitor to reduce voltage droop in a supply voltage in the second integrated circuit die during a high current event in the second integrated circuit die.

19. The circuit system of claim 18 further comprising:
a fourth integrated circuit die comprising a fourth state machine circuit and a third decoupling capacitor, w

Assignees

• Intel Corp
• Altera Corp

Inventors

• Srinivasan Archanna
• Gutala Ravi
• Weber Scott
• Dasu Aravind
• Iyer Mahesh
• Nurvitadhi Eriko

Classifications

• H10W90/00

  Package configurations · CPC title

• H03K19/17792

  for operating speed · CPC title

• H03K19/17728 Primary

  Reconfigurable logic blocks, e.g. lookup tables · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• H03K19/17772

  for powering on or off · CPC title