Interleaving scheme for increasing operating efficiency during high current events on an integrated circuit

Patent metadata

Field	Value
Publication number	US-10243561-B2
Application number	US-201715852814-A
Country	US
Kind code	B2
Filing date	Dec 22, 2017
Priority date	Dec 22, 2017
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

An integrated circuit configured to execute multiple operations in parallel is provided. The integrated circuit may be organized into multiple logic sectors. Two or more groups of logic sectors may be executed in an interleaved fashion, where successive groups of logic sectors are activated after a predetermined amount of delay. The integrated circuit may include an array of memory cells. Rows of the memory cells may be accessed in an interleaving manner, where successive rows of memory cells are selected after a predetermined amount of delay. Operating groups of circuit components using an interleaving scheme can help improve operational efficiency while reducing power supply noise without having to increase die area for on-die decoupling capacitance.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a first group of circuits configured to perform a first set of operations; and
a second group of circuits configured to start performing a second set of operations a predetermined amount of delay after the first group of circuits starts performing the first set of operations and before the first group of circuits finishes performing the first set of operations to prevent power supply voltage sag, wherein the first group of circuits and the second group of circuits have identical structure.

2. The integrated circuit of claim 1 , wherein the first set of operations and the second set of operations are identical.

3. The integrated circuit of claim 1 , wherein the first group of circuits comprises a first group of logic sectors, wherein the second group of circuits comprises a second group of logic sectors, wherein the first group of logic sectors start performing the first set of operations at a first point in time, and wherein the second group of logic sectors start performing the second set of operations at a second point in time before the first group of logic sectors finishes performing the first set of operations.

4. The integrated circuit of claim 3 , wherein the logic sectors in the first group are configured using a first set of logic sector managers, and wherein the logic sectors in the second group are configured using a second set of logic sector managers.

5. The integrated circuit of claim 4 , further comprising a secure device manager that is coupled to both the first and second sets of logic sector managers.

6. The integrated circuit of claim 1 , wherein the first group of circuits comprises a first row of random-access memory cells, and wherein the second group of circuits comprises a second row of random-access memory cells.

7. The integrated circuit of claim 6 , wherein the first set of operations comprises a first memory write operation on the first row of random-access memory cells that causes a first current spike event, and wherein the second set of operations comprises a second memory write operation on the second row of random-access memory cells that causes a second current spike event that occurs after the first current spike event.

8. The integrated circuit of claim 1 , further comprising additional groups of circuits having identical structure to the first and second groups of circuits, wherein the first, second, and additional groups of circuits are configured to perform identical operations using a two-way interleaving scheme.

9. The integrated circuit of claim 1 , further comprising additional groups of circuits having identical structure to the first and second groups of circuits, wherein the first, second, and additional groups of circuits are configured to perform identical operations using a four-way interleaving scheme.

10. A method of operating an integrated circuit that includes a first group of circuits and a second group of circuits, the method comprising:
using the first group of circuits to perform a first set of operations; and
using the second group of circuits to perform a second set of operations a predetermined amount of delay after the first group of circuits starts performing the first set of operations and before the first group of circuits finishes performing the first set of operations to prevent power supply voltage sag, wherein the first and second group of circuits are identical.

11. The method of claim 10 , wherein the first set of operations and the second set of operations are the same.

12. The method of claim 10 , wherein using the first group of circuits to perform the first set of operations comprises using a first group of logic sectors to perform a first set of logic functions, and wherein using the second group of circuits to perform the second set of operations comprises using a second group of logic sectors to perform a second set of logic functions.

13. The method of claim 12 , further comprising using logic sector managers to configure the first and second groups of logic sectors.

14. The method of claim 10 , wherein using the first group of circuits to perform the first set of operations comprises loading data into a first row of memory elements, and wherein using the second group of circuits to perform the second set of operations comprises loading data into a second row of memory elements.

15. The method of claim 10 , further comprising:
using a third group of circuits on the integrated circuit to perform a third set of operations the predetermined amount of delay after the second group of circuits starts performing the second set of operations and before the first and second groups of circuits finish performing the first and second sets of operations to prevent power supply voltage sag, wherein the first and third group of circuits are identical.

16. An integrated circuit, comprising:
a first group of circuits configured to perform a first set of logic functions causing a first high current event; and
a second group of circuits configured to perform a second set of logic functions causing a second high current event, wherein the first and second sets of logic functions are at least partially performed in parallel to increase operational efficiency, and wherein the first and second high current events are not aligned to prevent power supply voltage sag.

17. The integrated circuit of claim 16 , further comprising additional groups of circuits, wherein the first, second, and additional groups of circuits perform operations in a two-way interleaving fashion.

18. The integrated circuit of claim 16 , further comprising additional groups of circuits, wherein the first, second, and additional groups of circuits perform operations in a four-way interleaving fashion.

19. The integrated circuit of claim 16 , wherein the first and second groups of circuits comprise logic sectors, and wherein the logic sectors are configured by respective logic sector managers.

20. The integrated circuit of claim 16 , wherein the first group of circuits is configured to perform a third set of logic functions before the second group of circuits finishes performing the second set of logic functions.

Assignees

• Intel Corp

Inventors

• Srinivasan Archanna
• Chen Guang
• Tan Jun Pin

Classifications

• G11C7/00

  Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) · CPC title

• H03K19/1776

  for memories · CPC title

• H03K19/0008

  Arrangements for reducing power consumption · CPC title

• H03K19/00346 Primary

  Modifications for eliminating interference or parasitic voltages or currents · CPC title