Bond pads for semiconductor die assemblies and associated methods and systems

Patent metadata

Field	Value
Publication number	US-12255163-B2
Application number	US-202217666437-A
Country	US
Kind code	B2
Filing date	Feb 7, 2022
Priority date	Aug 12, 2021
Publication date	Mar 18, 2025
Grant date	Mar 18, 2025

Abstract

Bond pads for semiconductor die assemblies, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes a first semiconductor die including a first bond pad on a first side of the first semiconductor die. The semiconductor die assembly further includes a second semiconductor die including a second bond pad on a second side of the second semiconductor die. The first bond pad is aligned and bonded to the second bond pad at a bonding interface between the first and second bond pads, and at least one of the first and second bond pads include a first metal and a second metal different than the first metal. Further, the first metal is located at the bonding interface and the second metal has a first thickness corresponding to at least one-fourth of a second thickness of the first or second bond pad.

First claim

What is claimed is:

1. A semiconductor die assembly, comprising:
a first semiconductor die including a first bond pad on a first side of the first semiconductor die; and
a second semiconductor die including a second bond pad on a second side of the second semiconductor die, wherein:
the first bond pad is aligned and bonded to the second bond pad at a bonding interface therebetween; and
at least one of the first and second bond pads include a first copper layer having primarily a first crystallographic orientation and a second copper layer having primarily a second crystallographic orientation different than the first crystallographic orientation, the first copper layer located at the bonding interface,

wherein the first bond pad is connected to a through-substrate via (TSV) extending through the first semiconductor die and configured to couple the first bond pad to a conductive structure on a third side of the first semiconductor die, the third side opposite to the first side.

2. The semiconductor die assembly of claim 1 , wherein the first crystallographic orientation corresponds to (111) orientation.

3. The semiconductor die assembly of claim 1 , wherein the second copper layer has a first thickness corresponding to at least one-fourth of a second thickness of the first or second bond pad.

4. The semiconductor die assembly of claim 1 , wherein:
the first side of the first semiconductor die includes a first dielectric material around the first bond pad, the first dielectric material formed at a first temperature;
the second side of the second semiconductor die includes a second dielectric material around the second bond pad, the second dielectric material formed at a second temperature greater than the first temperature; and
the first and second dielectric materials are bonded at the bonding interface.

5. The semiconductor die assembly of claim 4 , wherein the first and second dielectric materials correspond to silicon carbon nitride.

6. The semiconductor die assembly of claim 1 , wherein the first and/or second semiconductor dies exchange electrical signals with a device external to the semiconductor assembly through the conductive structure.

7. The semiconductor die assembly of claim 1 , wherein the second bond pad is connected to a second through-substrate via (TSV) extending through the second semiconductor die and configured to couple the second bond pad to a third bond pad on a fourth side of the second semiconductor die, the fourth side opposite to the second side.

8. The semiconductor die assembly of claim 7 , wherein:
the fourth side of the second semiconductor die includes a first dielectric material around the third bond pad, the first dielectric material formed at a first temperature; and
the second side of the second semiconductor die includes a second dielectric material around the second bond pad, the second dielectric material formed at a second temperature greater than the first temperature.

9. The semiconductor die assembly of claim 7 , wherein:
the third bond pad is configured to bond with a fourth bond pad of a third semiconductor die of the semiconductor assembly at a second bonding interface; and
at least one of the third and fourth bond pads include a third copper layer having primarily the first crystallographic orientation and a fourth copper layer having primarily the second crystallographic orientation, the third copper layer located at the second bonding interface.

10. The semiconductor die assembly of claim 1 , wherein:
the first semiconductor die corresponds to a logic die or an interposer die; and
the second semiconductor die corresponds to a memory die.

11. A semiconductor die assembly, comprising:
a logic die including a first side and a second side opposite to the first side, wherein:
the first side includes integrated circuitry and conductive structures coupled thereto; and
the second side includes first bond pads operatively coupled with the conductive structures through through-substrate vias (TSVs) extending through the logic die; and

a memory die bonded at the second side of the logic die, the memory die including a frontside having a memory array and second bond pads operatively coupled with the memory array, wherein:
individual second bond pads are aligned and bonded to corresponding first bond pads at a bonding interface between the memory die and the logic die; and
the first, second, or both first and second bond pads include a first copper layer having primarily a first crystallographic orientation and a second copper layer having primarily a second crystallographic orientation different than the first crystallographic orientation, the first copper layer located at the bonding interface.

12. The semiconductor die assembly of claim 11 , wherein:
the memory die comprises third bond pads disposed on a backside of the memory die opposite to the frontside, the third bond pads coupled to the second bond pads through through-substrate vias (TSVs) extending through the memory die;
the third bond pads are surrounded with a first dielectric material formed at a first temperature; and
the second bond pads are surrounded with a second dielectric material formed at a second temperature greater than the first temperature.

13. The semiconductor die assembly of claim 12 , wherein the memory die is a first memory die, the semiconductor assembly further comprises:
a second memory die including fourth bond pads at a frontside of the second memory die having a second memory array operatively coupled with the fourth bond pads, wherein:
individual third bond pads are aligned and bonded to corresponding fourth bond pads at a second bonding interface between the first and second memory dies; and
the third, fourth, or both third and fourth bond pads include a third copper layer having primarily the first crystallographic orientation and a fourth copper layer having primarily the second crystallographic orientation, the third copper layer located at the second bonding interface.

Assignees

• Micron Technology Inc

Inventors

• Bhushan Bharat
• Singh Akshay N
• Kawakita Keizo
• Street Bret K

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W72/953

  not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids · CPC title