Graphene liners and caps for semiconductor structures

Patent metadata

Field	Value
Publication number	US-12255144-B2
Application number	US-202217647624-A
Country	US
Kind code	B2
Filing date	Jan 11, 2022
Priority date	Nov 12, 2021
Publication date	Mar 18, 2025
Grant date	Mar 18, 2025

Abstract

A graphene liner deposited between at least one liner material (e.g., barrier layer, ruthenium liner, and/or cobalt liner) and a copper conductive structure reduces surface scattering at an interface between the at least one liner material and the copper conductive structure. Additionally, or alternatively, the carbon-based liner reduces contact resistance at an interface between the at least one liner material and the copper conductive structure. A carbon-based cap may additionally or alternatively be deposited on a metal cap, over the copper conductive structure, to reduce surface scattering at an interface between the metal cap and an additional copper conductive structure deposited over the metal cap.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a copper conductive structure formed in a dielectric layer and below at least one etch stop layer (ESL); and
a bi-layer liner adjacent to the copper conductive structure, where in the bi-layer liner comprises a first layer of graphene adjacent to the copper conductive structure and a second layer adjacent to the first layer and at an interface between the copper conductive structure and a first conductive structure below the copper conductive structure,
wherein a ratio of a thickness of the second layer to a thickness of the first layer of graphene is in a range from approximately two to approximately twenty.

2. The semiconductor structure of claim 1 , wherein the first layer of graphene comprises no more than seven two-dimensional sheets of carbon atoms and has a thickness of no more than 20 Angstroms (Å).

3. The semiconductor structure of claim 1 , wherein the second layer comprises ruthenium, a nitride, or a combination thereof.

4. The semiconductor structure of claim 1 , wherein the second layer comprises a nitride doped with ruthenium.

5. The semiconductor structure of claim 1 , further comprising:
a cobalt liner adjacent to the second layer.

6. The semiconductor structure of claim 1 , further comprising:
an additional layer of graphene at an interface between the copper conductive structure and a second conductive structure above the copper conductive structure.

7. The semiconductor structure of claim 6 , further comprising:
a cap layer of cobalt at an interface between the copper conductive structure and a second conductive structure above the copper conductive structure, wherein a top surface of the layer of cobalt extends above a top surface of the dielectric layer.

8. The semiconductor structure of claim 6 , further comprising:
a cap layer of cobalt at an interface between the copper conductive structure and a second conductive structure above the copper conductive structure, wherein a bottom surface of the layer of cobalt extends below a top surface of the dielectric layer.

9. The semiconductor structure of claim 1 , wherein the second layer comprises a ruthenium liner.

10. The semiconductor structure of claim 1 , wherein the second layer comprises a cobalt liner.

11. A method, comprising:
forming a recess in a dielectric layer above a first conductive structure;
forming at least one liner material on sidewalls and a bottom surface of the recess;
forming a first graphene layer over the at least one liner material;
forming a copper conductive structure in the recess;
selectively depositing a layer of cobalt on a top surface of the copper conductive structure using an organic precursor;
removing the organic precursor using plasma after depositing the layer of cobalt; and
forming a second graphene layer on the layer of cobalt.

12. The method of claim 11 , wherein the second graphene layer is selectively deposited using a precursor comprising hydrocarbons.

13. The method of claim 11 , further comprising:
planarizing the copper conductive structure before forming the layer of cobalt.

14. The method of claim 11 , wherein a ratio of an amount of time associated with depositing the first graphene layer to an amount of time associated with depositing the at least one liner material is in a range from approximately one to approximately two.

15. The method of claim 11 , wherein forming the at least one liner material comprises:
forming a first layer including a nitride; and
forming a second layer including ruthenium.

16. The method of claim 11 , wherein forming the at least one liner material comprises:
forming a layer including a nitride; and
doping the layer of nitride with ruthenium.

17. A semiconductor structure, comprising:
a copper conductive structure formed in a dielectric layer and below at least one etch stop layer (ESL);
at least one liner material adjacent to sidewalls of the copper conductive structure and at an interface between the copper conductive structure and a first conductive structure below the copper conductive structure;
a bi-layer cap at an interface between the copper conductive structure and a second conductive structure above the copper conductive structure, wherein the bi-layer cap comprises a first layer adjacent to the copper conductive structure and a second layer of graphene adjacent to the first layer and at the interface between the copper conductive structure and the second conductive structure; and
an additional layer of graphene adjacent to the copper conductive structure.

18. The semiconductor structure of claim 17 , wherein a ratio of a thickness of the first layer to a thickness of the at least one liner material is in a range from approximately 0.2 to approximately 1.4.

19. The semiconductor structure of claim 17 , wherein a ratio of a thickness of the dielectric layer to a thickness of the at least one ESL is in a range from approximately two to approximately four.

20. The semiconductor structure of claim 17 , wherein the additional layer of graphene comprises a graphene liner.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chin Shu-Cheng
• Chang Chih-Yi
• Chi Chih-Chien
• Tsai Ming-Hsing

Classifications

• H10W20/0372

  comprising multiple barrier, adhesion or liner layers · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title