Semiconductor device and layout method of the same

Patent metadata

Field	Value
Publication number	US-12255140-B2
Application number	US-202217867195-A
Country	US
Kind code	B2
Filing date	Jul 18, 2022
Priority date	Oct 21, 2021
Publication date	Mar 18, 2025
Grant date	Mar 18, 2025

Abstract

A semiconductor device, includes a plurality of semiconductor elements, each of the plurality of semiconductor elements including a gate structure extending in a first direction and an active region provided on both sides of the gate structure in a second direction intersecting the first direction; and a plurality of interconnection patterns connected to the plurality of semiconductor elements, wherein the plurality of interconnection patterns include a plurality of upper interconnections provided above the plurality of semiconductor elements in a third direction, a plurality of intermediate interconnections provided between the plurality of semiconductor elements and the plurality of upper interconnections in the third direction, and a routing interconnection adjacent to at least one of the plurality of semiconductor elements in the second direction, wherein the routing interconnection is connected to at least one of the plurality of intermediate interconnections in the first direction or the second direction.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of semiconductor elements, each of the plurality of semiconductor elements including a gate structure extending in a first direction, parallel to an upper surface of a substrate, and an active region provided on both sides of the gate structure in a second direction intersecting the first direction; and
a plurality of interconnection patterns connected to the plurality of semiconductor elements,
wherein the plurality of interconnection patterns include:
a plurality of upper interconnections provided above the plurality of semiconductor elements in a third direction perpendicular to the upper surface of the substrate,
a plurality of intermediate interconnections provided between the plurality of semiconductor elements and the plurality of upper interconnections in the third direction, and
a routing interconnection extending in the first direction and adjacent to at least one of the plurality of semiconductor elements in the second direction, a length of the routing interconnection in the first direction is greater than a length of the active region in the first direction,
wherein the routing interconnection is connected to at least one of the plurality of intermediate interconnections in the first direction or the second direction.

2. The semiconductor device of claim 1 , further comprising
a plurality of contacts connecting each of the plurality of upper interconnections to at least one of the plurality of semiconductor elements,
wherein the plurality of intermediate interconnections and the routing interconnection are provided at a same height as the plurality of contacts in the third direction.

3. The semiconductor device of claim 1 , wherein the plurality of upper interconnections extend in the second direction,
wherein the plurality of upper interconnections comprise a first power interconnection overlapping a plurality of PMOS elements among the plurality of semiconductor elements, a second power interconnection overlapping a plurality of NMOS elements among the plurality of semiconductor elements, and a plurality of signal interconnections separated from the first power interconnection and the second power interconnection in the first direction.

4. The semiconductor device of claim 3 , wherein the routing interconnection is connected to at least one signal interconnection from the plurality of signal interconnections.

5. The semiconductor device of claim 4 , wherein the at least one signal interconnection connected to the routing interconnection is not provided between the first power interconnection and the second power interconnection in the first direction.

6. The semiconductor device of claim 1 , further comprising:
a PMOS element region in which a plurality of PMOS elements of the plurality of semiconductor elements are provided, an NMOS element region in which a plurality of NMOS elements of the plurality of semiconductor elements are provided, and an element isolation region, different from the PMOS element region and the NMOS element region,
wherein the PMOS element region, the NMOS element region, and the element isolation region are arranged in the first direction.

7. The semiconductor device of claim 6 , wherein the routing interconnection intersects at least one of the PMOS element region and the NMOS element region and extends in the first direction.

8. The semiconductor device of claim 7 , wherein the element isolation region comprises a first element isolation region provided between the PMOS element region and the NMOS element region in the first direction, a second element isolation region provided over the PMOS element region in the first direction, and a third element isolation region provided below the NMOS element region in the first direction,
wherein the routing interconnection is connected to at least one of the plurality of intermediate interconnections in the first element isolation region.

9. The semiconductor device of claim 8 , wherein the routing interconnection extends from the first element isolation region to the second element isolation region or the third element isolation region.

10. The semiconductor device of claim 8 , wherein the routing interconnection is connected to at least one of the plurality of upper interconnections in the second element isolation region or the third element isolation region.

11. The semiconductor device of claim 8 , further comprising:
a plurality of lower interconnections provided at a same height as the gate structure in the third direction, and provided in at least one of the second element isolation region and the third element isolation region,
wherein the routing interconnection is connected to at least one of the plurality lower interconnections in the second element isolation region or the third element isolation region.

12. The semiconductor device of claim 6 , wherein the gate structure included in at least one of the plurality of semiconductor elements comprises a gate tap structure extending from the first direction to the element isolation region, and extending from the element isolation region in the second direction.

13. A semiconductor device, comprising:
a plurality of standard cells arranged in a first direction and a second direction, the first and the second direction being parallel to an upper surface of a substrate and intersecting each other, and each of the plurality of standard cells including a plurality of semiconductor elements; and
a plurality of filler cells provided adjacent to one or more of the plurality of standard cells, the plurality of filler cells including a routing filler cell,
wherein the routing filler cell includes a routing interconnection connected, via an intermediate interconnection, to at least one of the plurality of semiconductor elements included in a neighboring standard cell that is adjacent to the routing filler cell in the second direction,
wherein the routing interconnection extends in the first direction parallel to a gate structure of each of the plurality of semiconductor elements, and
wherein the intermediate interconnection and the routing interconnection are provided at a same height as contacts connected to the plurality of semiconductor elements.

14. The semiconductor device of claim 13 , further comprising,
a plurality of upper interconnections extending in the second direction are provided above the plurality of semiconductor elements in a third direction perpendicular to the upper surface of the substrate,
wherein the plurality of upper interconnections include a plurality of power interconnections for supplying a power voltage and a plurality of signal interconnections provided at first positions different from second positions at which the plurality of power supply interconnections are provided,
wherein the intermediate interconnection is provided below the signal interconnections.

15. The semiconductor device of claim 14 , wherein the routing interconnection extends in the first direction below at least one of the plurality of power interconnections.

16. The semiconductor device of claim 14 , wherein a first width of each of the plurality of power interconnections in the first direction is greater than a second width of each of the plurality of signal interconnections in the first direction.

17. The semiconductor device of claim 14 , wherein the plurality of power interconnections comprise a first power interconnection for supplying a first power voltage, and a second power line for supplying a second power voltage, lower than the first power vo

Assignees

• Samsung Electronics Co Ltd

Inventors

• Chai Seungil
• Shin Kyunghee
• Lee Daehee
• Lee Moonhui

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title