Embedded package with electrically isolating dielectric liner

Patent metadata

Field	Value
Publication number	US-12255114-B2
Application number	US-202318390603-A
Country	US
Kind code	B2
Filing date	Dec 20, 2023
Priority date	Oct 27, 2021
Publication date	Mar 18, 2025
Grant date	Mar 18, 2025

Abstract

A method of forming a semiconductor package includes producing a package substrate that includes an interior laminate layer, a first metallization layer disposed below the interior laminate layer, and a second metallization layer disposed above the interior laminate layer, providing a first load terminal on a first surface of the first semiconductor die and a second load terminal on a second surface of the first semiconductor die; and a liner of dielectric material on the first semiconductor die; providing a liner of dielectric material on the first semiconductor die; embedding the first semiconductor die within the interior laminate layer such that the first surface of the first semiconductor die faces the second metallization layer, and wherein the liner of dielectric material is disposed on a corner of the first semiconductor die that is between the first and second load terminals of the first semiconductor die.

First claim

The invention claimed is:

1. A method of forming a semiconductor package, the method comprising:
producing a package substrate that comprises an interior laminate layer, a first metallization layer disposed below the interior laminate layer, and a second metallization layer disposed above the interior laminate layer;
providing a first semiconductor die with a first load terminal disposed on a first surface of the first semiconductor die and a second load terminal disposed on a second surface of the first semiconductor die that is opposite from the first surface of the first semiconductor die; and
providing a liner of dielectric material on the first semiconductor die;
embedding the first semiconductor die within the interior laminate layer such that the first surface of the first semiconductor die faces the second metallization layer, and
wherein the liner of dielectric material is disposed on a corner of the first semiconductor die that is between the first and second load terminals of the first semiconductor die.

2. The method of claim 1 , wherein the first semiconductor die is provided with the liner of dielectric material disposed on the corner of the first semiconductor die prior to the embedding of the first semiconductor die.

3. The method of claim 2 , wherein the corner of the first semiconductor die is between the first surface of the first semiconductor die and a first edge side of the first semiconductor die that extends between the first and second surfaces of the first semiconductor die, and wherein the liner of dielectric material comprises a first part that is disposed on the first surface of the first semiconductor die and extends from the first load terminal to the corner.

4. The method of claim 3 , wherein the liner of dielectric material comprises a second part that is disposed on the first edge side and extends from the corner along only a portion of the first edge side.

5. The method of claim 1 , wherein embedding the first semiconductor die in the interior laminate layer comprises:
providing a core structure comprising a plurality of openings;
arranging the first semiconductor die comprising the liner of dielectric material disposed on the corner of the first semiconductor die within one of the openings; and
filling gaps in the openings between the first semiconductor die and the core structure with dielectric material.

6. The method of claim 5 , further comprising:
providing a second semiconductor die that comprises a first load terminal disposed on a first surface of the second semiconductor die and a second load terminal disposed on a second surface of the second semiconductor die that is opposite from the first surface of the second semiconductor die;
providing a liner of dielectric material on the second semiconductor die; and
embedding the second semiconductor die is within the interior laminate layer such that the first surface of the first semiconductor die faces the first metallization layer,
wherein the liner of dielectric material is disposed on a corner of the second semiconductor die that is between the first and second load terminals of the second semiconductor die, and
wherein the second semiconductor die is provided with the liner of dielectric material disposed on the corner of the second semiconductor die prior to the embedding of the second semiconductor die.

7. The method of claim 6 , wherein the semiconductor package is configured as an integrated half-bridge circuit, wherein the first and second semiconductor dies are each configured as discrete power transistor dies, wherein the first semiconductor die is a high-side switch of the integrated half-bridge circuit, and wherein the second semiconductor die is a low-side switch of the integrated half-bridge circuit.

8. The method of claim 7 , wherein the first load terminal of the first semiconductor die is a source terminal of the high-side switch, wherein the second load terminal of the second semiconductor die is a drain terminal of the low-side switch, and wherein the first load terminal of the first semiconductor die is electrically connected to the second load terminal of the second semiconductor die by the second metallization layer.

Assignees

• Infineon Technologies Ag

Inventors

• Cho Eung San

Classifications

• H10W72/9413

  on encapsulations · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W90/00 Primary

  Package configurations · CPC title