Memory device including switching material and phase change material

Patent metadata

Field	Value
Publication number	US-12254922-B2
Application number	US-202318157408-A
Country	US
Kind code	B2
Filing date	Jan 20, 2023
Priority date	Aug 4, 2022
Publication date	Mar 18, 2025
Grant date	Mar 18, 2025

Abstract

A memory device includes a memory cell including a selection layer and a phase change material layer, and a controller, wherein the selection layer includes a switching material, the phase change material layer includes a phase change material, and the controller is configured to apply a write pulse to the selection layer and the phase change material layer and control a polarity, a peak value, and a shape of the write pulse.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell including a selection layer and a phase change material layer connected in series, the selection layer comprising a switching material and the phase change material layer comprising a phase change material; and
a controller configured to control a polarity, a peak value, and a shape of write pulses applied to the memory cell to change a resistance of the selection layer, to change a resistance of the phase change material, and to change the resistances of both the selection layer and the phase change material,
wherein the switching material is configured such that the resistance of the switching material is changed according to at least one of the polarity or peak value of the applied write pulse, and
wherein the phase change material is configured such that the resistance of the phase change material is changed according to the shape of the applied write pulse.

2. The memory device of claim 1 , wherein the controller is further configured to adjust a resistance of the phase change material by controlling a fall time length of the write pulses.

3. The memory device of claim 1 , wherein the controller is configured to control an application of a first write pulse to the memory cell,
wherein the first write pulse includes a negative polarity, a first peak value, and a rectangular shape.

4. The memory device of claim 3 , wherein, after the first write pulse, the memory cell has a first logic state in which both the switching material and the phase change material have a first high resistance when the first write pulse is applied to the memory cell.

5. The memory device of claim 4 , wherein the controller is configured to control an application of a second write pulse to the memory cell,
wherein the second write pulse includes the negative polarity, a second peak value less than the first peak value, and a rectangular shape.

6. The memory device of claim 5 , wherein, after the second write pulse, the memory cell has a second logic state in which both the switching material and the phase change material have a second high resistance when the second write pulse is applied to the memory cell and the second high resistance is less than the first high resistance.

7. The memory device of claim 5 , wherein the controller is configured to control an application of a third write pulse to the memory cell,
wherein the third write pulse includes a positive polarity, a second peak value less than the first peak value, and a rectangular shape.

8. The memory device of claim 7 , wherein, after the third write pulse, the memory cell has a third logic state in which the switching material has a low resistance and the phase change material has a first high resistance when the third write pulse is applied to the memory cell.

9. The memory device of claim 7 , wherein the controller is configured to control an application of a fourth write pulse to the memory cell,
wherein the fourth write pulse includes the negative polarity, a second peak value less than the first peak value, and a trapezoidal shape.

10. The memory device of claim 9 , wherein, after the fourth write pulse, the memory cell has a fourth logic state in which the switching material has a second high resistance and the phase change material has a low resistance when the fourth write pulse is applied to the memory cell, and the second high resistance is less than the first high resistance.

11. The memory device of claim 9 , wherein the controller is configured to control an application of a fifth write pulse to the memory cell,
wherein the fifth write pulse includes a positive polarity, a second peak value less than the first peak value, a first fall time length, and a trapezoidal shape.

12. The memory device of claim 11 , wherein, after the fifth write pulse, the memory cell has a fifth logic state in which both the switching material and the phase change material have a low resistance when the fifth write pulse is applied to the memory cell.

13. The memory device of claim 12 , wherein the controller is configured to control an application of a sixth write pulse to the memory cell,
wherein the sixth write pulse includes the positive polarity, a third peak value less than the first peak value, a second fall time length greater than the first fall time length, and a trapezoidal shape.

14. The memory device of claim 13 , wherein, after the sixth write pulse, the memory cell has a sixth logic state in which the switching material has a low resistance and the phase change material has a lower resistance compared to the fifth logic state.

15. The memory device of claim 1 , wherein the switching material includes a chalcogenide material,
wherein the chalcogenide material includes
a first element including germanium (Ge),
a second element including at least one of arsenic (As) or antimony (Sb),
a third element including at least one of tellurium (Te), selenium (Se), or sulfur(S), and
a fourth element including at least one of indium (In), aluminum (Al), carbon (C), boron (B), strontium (Sr), gallium (Ga), oxygen (O), nitrogen (N), silicon (Si), calcium (Ca), or phosphorus (P).

16. The memory device of claim 1 , wherein the phase change material includes a chalcogenide material,
wherein the chalcogenide material includes
a first element including germanium (Ge),
a second element including at least one of arsenic (As) or antimony (Sb),
a third element including at least one of tellurium (Te), selenium (Se), or sulfur(S), and
a fourth element including at least one of indium (In), aluminum (Al), carbon (C), boron (B), strontium (Sr), gallium (Ga), oxygen (O), nitrogen (N), silicon (Si), calcium (Ca), or phosphorus (P).

17. A memory device comprising:
a selection layer including a switching material;
a phase change material layer connected in series with the selection layer; and
a controller configured to control an application, to the selection layer and the phase change material layer, of a first write pulse having a first polarity and a first fall time length and of a second write pulse having a second polarity opposite to the first polarity and a second fall time length different from the first fall time length,
wherein the switching material is configured such that a resistance of the switching material is changed according to at least one of a polarity or peak value of an applied write pulse, and
wherein the phase change material is configured such that a resistance of the phase change material is changed according to a shape of the applied write pulse.

18. The memory device of claim 17 , wherein the first write pulse has a first peak value, and the second write pulse has a second peak value different from the first peak value.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Minwoo
• Kang Young Jae
• Koo Bonwon
• Park Yongyoung
• Sung Hajun
• Ahn Dongho
• Yang Kiyeon
• Yang Wooyoung
• Lee Changseung

Classifications

• H10B63/10

  Phase change RAM [PCRAM, PRAM] devices · CPC title

• G11C2213/30

  Resistive cell, memory material aspects · CPC title

• H10B63/84

  arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• H10N70/882

  Compounds of sulfur, selenium or tellurium, e.g. chalcogenides · CPC title