Front-end for receivers with RF sampling ADCS

Patent metadata

Field	Value
Publication number	US-12250015-B2
Application number	US-202217903970-A
Country	US
Kind code	B2
Filing date	Sep 6, 2022
Priority date	Sep 7, 2021
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

Front-end circuitry is difficult to design for high sample rate, wide bandwidth receivers with high performance requirements on noise and linearity. One exemplary front-end circuitry is integrated on-chip with the RF ADC in a receiver, and the circuitry implements ESD protection, attenuation, and gain. The circuitry includes a multi-tap filter with LC circuits, and the filter implements a highly linear filter. Advantageously, the capacitors in the LC circuits are also used for ESD protection. Additionally, tunable attenuator cells are implemented across the multi-tap filter to provide a wide range of variable attenuation. The circuitry can further include a fixed or variable gain stage at the output. The resulting circuitry offers variable gain and attenuation while meeting bandwidth, noise, and linearity requirements.

First claim

What is claimed is:

1. A front-end at an input of a radio-frequency analog-to-digital converter of a receiver, the front-end comprising:
a multi-tap filter comprising inductor-capacitor circuits;
attenuator cells distributed across taps of the multi-tap filter;
electrostatic discharge protection circuitry integrated with the multi-tap filter, wherein the electrostatic discharge protection circuitry comprises a first segment upstream of a first inductor of the multi-tap filter, and a second segment downstream of the first inductor; and
a gain stage at an output of the multi-tap filter.

2. The front-end of claim 1 , wherein the multi-tap filter includes five shunt capacitors and four inductors.

3. The front-end of claim 1 , wherein the multi-tap filter implements a 9 th order symmetrical Chebyshev filter.

4. The front-end of claim 1 , wherein one or more ones of the attenuator cells has programmable attenuation.

5. The front-end of claim 1 , wherein one or more ones of the attenuator cells is switchable to be on or off.

6. The front-end of claim 1 , wherein the attenuator cells comprises one attenuator cell having a Π-topology and three attenuator cells having a T-topology.

7. The front-end of claim 1 , wherein each attenuator cell includes a series resistance and a shunt resistance.

8. The front-end of claim 1 , wherein each attenuator cell includes a bypass switch to short input and output nodes of the attentuator cell.

9. The front-end of claim 1 , wherein the front-end is on-chip with the radio-frequency analog-to-digital converter.

10. The front-end of claim 1 , wherein the attenuator cells are tunable based on an automatic gain control signal.

11. The front-end of claim 1 , wherein the gain stage provides a variable gain based on an automatic gain control signal.

12. A front-end at an input of a radio-frequency analog-to-digital converter of a receiver, the front-end comprising:
a multi-tap filter comprising inductor-capacitor circuits;
attenuator cells distributed across taps of the multi-tap filter, wherein the attenuator cells comprise a first attenuator cell, the first attenuator cell comprising:
at least one transistor having a bootstrapped gate to provide a series resistance;
a shunt path to provide a shunt resistance, the shunt path comprising a shunt transistor; and
a bypass switch comprising a bypass transistor having a gate driven by a control signal, wherein the bypass transistor shorts an input node of the first attenuator cell and an output node of the first attenuator cell when the bypass transistor is on;

electrostatic discharge protection circuitry integrated with the multi-tap filter; and
a gain stage at an output of the multi-tap filter.

13. The front-end of claim 12 , wherein the at least one transistor is biased to be constantly on during operation.

14. The front-end of claim 12 , wherein the at least one transistor is bootstrapped to the input of the first attenuator cell.

15. The front-end of claim 12 , wherein the bypass transistor is bootstrapped to an input of the first attenuator cell.

16. The front-end of claim 12 , wherein the shunt transistor is bootstrapped to a drain of the shunt transistor.

17. The front-end of claim 12 , wherein the electrostatic discharge protection circuitry comprises a first segment upstream of a first inductor of the multi-tap filter, and a second segment downstream of the first inductor.

18. A front-end at an input of a radio-frequency analog-to-digital converter of a receiver, the front-end comprising:
a multi-tap filter comprising inductor-capacitor circuits;
attenuator cells distributed across taps of the multi-tap filter;
electrostatic discharge protection circuitry integrated with the multi-tap filter;
a gain stage at an output of the multi-tap filter; and
a termination resistor coupled to an input of the gain stage, wherein the front end is differential, and wherein the termination resistor has a resistance of less than 100Ω,
wherein the front-end is on-chip with the radio-frequency analog-to-digital converter, and
wherein the front-end has a bandwidth of greater than 30 gigahertz.

19. The front-end of claim 18 , wherein the resistance of the termination resistor is 50 Ω.

20. The front-end of claim 18 , further A front-end at an input of a radio-frequency analog-to-digital converter of a receiver, the front-end comprising:
a multi-tap filter comprising inductor-capacitor circuits;
attenuator cells distributed across taps of the multi-tap filter;
electrostatic discharge protection circuitry integrated with the multi-tap filter;
a gain stage at an output of the multi-tap filter; and
a termination resistor coupled to an input of the gain stage, wherein the front end is single-ended, and wherein the termination resistor has a resistance of less than 50Ω,
wherein the front-end is on-chip with the radio-frequency analog-to-digital converter, and
wherein the front-end has a bandwidth of greater than 30 gigahertz.

21. The front-end of claim 20 , wherein the resistance of the termination resistor is 25 Ω.

Assignees

• Analog Devices International Unlimited Co

Inventors

• Ramkaj Athanasios
• Manganaro Gabriele
• Tavernier Filip
• Devarajan Siddharth

Classifications

• H04B1/1607 Primary

  Supply circuits (converters H02M; filters therefor H02M1/14; voltage stabilisers G05F1/46) · CPC title

• H04B1/1638

  Special circuits to enhance selectivity of receivers not otherwise provided for (resonant circuits H03H) · CPC title

• H04B1/18 Primary

  Input circuits, e.g. for coupling to an antenna or a transmission line (coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H) · CPC title