Transceiver circuit having a single impedance matching network

Patent metadata

Field	Value
Publication number	US-10141971-B1
Application number	US-201715815920-A
Country	US
Kind code	B1
Filing date	Nov 17, 2017
Priority date	Nov 17, 2017
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

Embodiments of transceiver circuits disclosed herein include a first amplifier coupled to receive signals from an antenna during a receive (RX) mode of the transceiver circuit, a second amplifier coupled to transmit signals to the antenna during a transmit (TX) mode of the transceiver circuit, and a single impedance matching network coupled to the antenna and directly connected to a shared node to which the first and second amplifiers are directly connected. The single impedance matching network is configured to transform an impedance of the antenna into a resistance at the shared node. A control circuit is coupled to control the impedance transformation of the single impedance matching network, so as to provide a first resistance at the shared node during RX mode and a second resistance at the shared node during TX mode, wherein the second resistance is different from the first resistance.

First claim

What is claimed is:

1. A transceiver circuit, comprising:
a first amplifier coupled to receive signals from an antenna during a receive (RX) mode of the transceiver circuit;
a second amplifier coupled to transmit signals to the antenna during a transmit (TX) mode of the transceiver circuit, wherein the first and second amplifiers are directly connected to a shared node;
a single impedance matching network coupled to the antenna, directly connected to the shared node, and configured to transform an impedance of the antenna into a resistance at the shared node, wherein the single impedance matching network comprises a multiple stage inductor-capacitor (LC) network including at least a first stage and a second stage cascaded with the first stage, wherein the first stage and the second stage each comprise at least one variable capacitor having a capacitance that is reconfigurable; and
a control circuit coupled to the single impedance matching network, and configured to control the capacitance of the variable capacitors included within the first and second stages to provide a first resistance at the shared node during RX mode and a second resistance at the shared node during TX mode:
wherein the first resistance is a resistance at an input of the first amplifier that achieves a maximum voltage gain at the input of the first amplifier;
wherein the second resistance is a resistance at an output of the second amplifier that achieves a maximum output power at the output of the second amplifier; and
wherein the second resistance is different from the first resistance.

2. The transceiver circuit as recited in claim 1 , wherein the transceiver circuit is time division duplex (TDD) transceiver, and wherein the TX and RX modes occur at different times.

3. The transceiver circuit as recited in claim 1 , wherein the first amplifier, the second amplifier and the single impedance matching network are provided on an integrated circuit (IC) chip, wherein the antenna is not provided on the IC chip, and wherein the single impedance matching network is coupled to the antenna via a single input/output (I/O) pad of the IC chip.

4. The transceiver circuit as recited in claim 3 , wherein the single impedance matching network is directly connected to the single I/O pad of the IC chip and directly connected to the shared node.

5. The transceiver circuit as recited in claim 1 , wherein the single impedance matching network comprises a plurality of reactive elements, and wherein the plurality of reactive elements comprise at least one variable reactive element having a reactance that is reconfigurable to provide the first resistance at the shared node during RX mode and the second resistance at the shared node during TX mode.

6. The transceiver circuit as recited in claim 1 , wherein the first stage and the second stage each comprise a series inductor and a variable capacitor coupled to the series inductor in an L-network configuration.

7. The transceiver circuit as recited in claim 1 , wherein the first stage comprises a series inductor and a first variable capacitor, which is coupled to a center tap point of the series inductor, and wherein the second stage comprises a second variable capacitor coupled to the series inductor in an L-network configuration.

8. The transceiver circuit as recited in claim 1 , wherein the first stage comprises a series inductor and a plurality of variable capacitors, each coupled to a different tap point of the series inductor, and wherein the second stage comprises an additional variable capacitor coupled to the series inductor in an L-network configuration.

9. The transceiver circuit as recited in claim 1 , wherein the first stage and the second stage each comprise a series capacitor and a shunt inductor, and wherein the first stage and the second stage each further comprise a variable capacitor, which is coupled in parallel with the shunt inductor.

10. The transceiver circuit as recited in claim 1 , wherein the control circuit uses two or more sets of predetermined values to control the capacitance of the variable capacitors included within the first and second stages.

11. The transceiver circuit as recited in claim 10 , wherein the control circuit comprises a memory element for storing the two or more sets of predetermined values.

12. The transceiver circuit as recited in claim 10 , wherein the two or more sets of predetermined values comprise:
a first set of predetermined values used during RX mode to control the capacitance of the variable capacitors included within the first and second stages to transform the impedance of the antenna into the first resistance; and
a second set of predetermined values used during TX mode to control the capacitance of the variable capacitors included within the first and second stages to transform the impedance of the antenna into the second resistance; and
wherein the second set of predetermined values differ from the first set of predetermined values.

13. The transceiver circuit as recited in claim 12 , wherein the two or more sets of predetermined values further comprise a third set of predetermined values used during TX mode to control the capacitance of the variable capacitors included within the first and second stages to transform the impedance of the antenna into a third resistance, which is greater than the second resistance.

14. A method for configuring a single impedance matching network shared by a first amplifier in a receive path and a second amplifier in a transmit path of a transceiver circuit, wherein the single impedance matching network comprises a two-stage inductor-capacitor (LC) network, wherein a first stage of the LC network and a second stage of the LC network each comprise at least one variable capacitor, and wherein the method comprises:
determining a first set of capacitance values for configuring the variable capacitors included within the first and second stages of the LC network, wherein the first set of capacitance values is subsequently used during a receive mode of the transceiver circuit to transform an antenna impedance into a first resistance at an input of the first amplifier that achieves a maximum voltage gain at an input of the first amplifier;
determining a second set of capacitance values for configuring the variable capacitors included within the first and second stages of the LC network, wherein the second set of capacitance values is subsequently used during a transmit mode of the transceiver circuit to transform the antenna impedance into a second resistance at an output of the second amplifier that achieves a maximum output power at an output of the second amplifier;
wherein the second resistance is different from the first resistance; and
wherein the second set of capacitance values differ from the first set of capacitance values.

15. The method as recited in claim 14 , wherein said determining a first set of capacitance values comprises setting a first variable capacitor in the first stage to a minimum capacitance value and determining a maximum capacitance value of a second variable capacitor in the second stage, wherein the maximum capacitance value is proportional to a quality factor of the LC network and inversely proportional to a maximum resistance of the LC network.

16. The method as recited in claim 14 , wherein said determining a second set of capacitance values comprises determining a first capacitance value of a first variable capacitor in the first stage of the LC network for transforming the impedance of the antenna into an intermediate resistance, wherein the first capacitance value is proporti

Assignees

• Silicon Lab Inc

Inventors

• Elkholy Mohamed
• Shafik Ayman
• Gao Yang
• Mukherji Arup
• Harwalkar Navin

Classifications

• H04B7/2615 Primary

  using hybrid frequency-time division multiple access [FDMA-TDMA] · CPC title

• H04B1/40 Primary

  Circuits · CPC title

• H04B1/48

  in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter {(H04B1/46 takes precedence)} · CPC title

• H04B1/0458

  Arrangements for matching and coupling between power amplifier and antenna or between amplifying stages (matching circuits in general H03H) · CPC title

• H04B1/18

  Input circuits, e.g. for coupling to an antenna or a transmission line (coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H) · CPC title