Ternary inverter and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12249605-B2
Application number	US-202217673754-A
Country	US
Kind code	B2
Filing date	Feb 16, 2022
Priority date	Jun 30, 2021
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

Provided are an inverter including a first source and drain, an interlayer insulating film on the first source, a second source on the interlayer insulating film, a second drain on the first drain, a first channel between the first source and drain, a second channel over the first channel between the second source and drain, a gate insulating film covering outer surfaces of the first and second channel, a part of a surface of the first source in the direction to the first drain, a part of a surface of the second source in the direction to the second drain, a part of a surface of the first drain in the direction to the first source, and a part of a surface of the second drain in the direction to the second source, and a gate electrode between the first source and drain and between the second source and drain.

First claim

What is claimed is:

1. A ternary inverter comprising:
a first source and a first drain apart from each other;
an interlayer insulating film on the first source;
a second source on the interlayer insulating film and a second drain on the first drain;
a first channel positioned between the first source and the first drain and having a 1 st -1 st end surface in a direction to the first source and a 1 st -2 nd end surface in a direction to the first drain, wherein the 1 st -1 st end surface is in contact with the first source, and the 1 st -2 nd end surface is in contact with the first drain;
a second channel disposed over the first channel to be apart from the first channel, positioned between the second source and the second drain, and having a 2 nd -1 st end surface in a direction to the second source and a 2 nd -2 nd end surface in a direction to the second drain, wherein the 2 nd -1 st end surface is in contact with the second source, and the 2 nd -2 nd end surface is in contact with the second drain;
a gate insulating film covering an outer surface of the first channel, an outer surface of the second channel, a part of a surface of the first source in the direction to the first drain, the part other than a portion thereof in contact with the first channel, a part of a surface of the second source in the direction to the second drain, the part other than a portion thereof in contact with the second channel, a part of a surface of the first drain in the direction to the first source, the part other than a portion thereof in contact with the first channel, and a part of a surface of the second drain in the direction to the second source, the part other than a portion thereof in contact with the second channel;
a gate electrode between the first source and the first drain and between the second source and the second drain; and
a constant current forming layer, wherein the first source and the first drain are disposed on the constant current forming layer.

2. The ternary inverter of claim 1 , wherein the first source is doped with a conductivity type which is different from a conductivity type with which the second source is doped.

3. The ternary inverter of claim 2 , wherein the first drain is doped with a conductivity type which is different from a conductivity type with which the first source is doped.

4. The ternary inverter of claim 2 , wherein the first drain is doped with a conductivity type which is different from a conductivity type with which the second drain is doped.

5. The ternary inverter of claim 1 , wherein the gate electrode fills a space between the first channel and the second channel.

6. The ternary inverter of claim 5 , wherein the gate electrode surrounds a first portion of the gate insulating film, the first portion surrounding the first channel, and a second portion of the gate insulating film, the second portion surrounding the second channel.

7. A method of manufacturing a ternary inverter, the method comprising:
forming a gate structure on a substrate, the gate structure extending in a first direction and including a first sacrificial layer, a first channel on the first sacrificial layer, a second sacrificial layer on the first channel, a second channel on the second sacrificial layer, and a third sacrificial layer on the second channel;
forming a dummy gate extending in a second direction intersecting the first direction such that the dummy gate crosses the gate structure;
forming a first source in contact with a 1 st -1 st end surface of the first channel on one side of the dummy gate and forming a first drain in contact with a 1 st -2 nd end surface of the first channel on the other side of the dummy gate;
forming an interlayer insulating film on the first source;
forming a second source in contact with a 2 nd -1 st surface of the second channel on the interlayer insulating film and forming a second drain in contact with a 2 nd -2 nd end surface of the second channel on the first drain;
removing the dummy gate;
removing the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer;
forming a gate insulating film covering an outer surface of the first channel, an outer surface of the second channel, a part of a surface of the first source in a direction to the first drain, the part other than a portion thereof in contact with the first channel, a part of a surface of the second source in a direction to the second drain, the part other than a portion thereof in contact with the second channel, a part of a surface of the first drain in a direction to the first source, the part other than a portion thereof in contact with the first channel, and a part of a surface of the second drain in a direction to the second source, the part other than a portion thereof in contact with the second channel; and
forming a gate electrode between the first source and the first drain and between the second source and the second drain; and
forming a constant current forming layer, wherein the first source and the first drain are disposed on the constant current forming layer.

8. The method of claim 7 , further comprising doping the first source and the first drain with different conductivity types.

9. The method of claim 8 , further comprising doping the second source with a conductivity type different from that of the first source, and doping the second drain with a conductivity type different from that of the first drain.

10. The method of claim 7 , wherein the forming of the gate electrode comprises forming the gate electrode to fill a space where the dummy gate is removed between the first source and the first drain and between the second source and the second drain.

11. The method of claim 7 , wherein the forming of the gate electrode comprises forming the gate electrode to surround a first portion of the gate insulating film, the first portion surrounding the first channel, and a second portion of the gate insulating film, the second portion surrounding the second channel.

Assignees

• Ulsan Nat Inst Science & Tech Unist

Inventors

• Kim Kyung Rok
• Jeong Jae Won
• Choi Youngeun
• Kim Wooseok

Classifications

• H10P14/3452

  Microstructure · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/038 Primary

  using silicon technology, e.g. SiGe · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title