System on chip and display device

Patent metadata

Field	Value
Publication number	US-12249277-B2
Application number	US-202418589431-A
Country	US
Kind code	B2
Filing date	Feb 28, 2024
Priority date	Apr 4, 2023
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

The present disclosure provides an system on chip and a display device. The system on chip includes a shared storage unit, a micro-processing unit, a display calibration unit, and an image processing unit. In response to a calibration instruction, the display calibration unit obtain image sampling data in the shared storage unit to perform a compensation computation operation and generate optical compensation data. In response to a display instruction, the image processing unit obtains display configuration data and the optical compensation data in the shared storage unit to perform a picture compensation operation.

First claim

What is claimed is:

1. A system on chip for connection with an active light-emitting display panel, comprising:
a shared storage unit configured to store image sampling data, display configuration data, and optical compensation data;
a micro-processing unit connected to the shared storage unit, wherein the micro-processing unit is configured to receive a control signal and output a control instruction in response to the control signal to trigger enablement of the shared storage unit, the control instruction comprising one of a display instruction and a calibration instruction;
a display calibration unit connected to the micro-processing unit, wherein the display calibration unit is configured to, in response to the calibration instruction, obtain the image sampling data in the shared storage unit to perform a compensation computation operation and generate the optical compensation data; and
an image processing unit connected to the micro-processing unit, wherein the image processing unit is configured to, in response to the display instruction, obtain the display configuration data and the optical compensation data in the shared storage unit to perform a picture compensation operation.

2. The system on chip according to claim 1 , wherein the shared storage unit comprises at least one random access memory connected to the micro-processing unit, and
the micro-processing unit is configured to release the random access memory when the display calibration unit finishes the compensation computation operation or when the image processing unit finishes the picture compensation operation.

3. The system on chip according to claim 2 , wherein the shared storage unit further comprises a non-volatile memory, and the non-volatile memory and the random access memory are respectively connected to the micro-processing unit;
the non-volatile memory is configured to store the image sampling data, the display configuration data, and the optical compensation data; and
the micro-processing unit is configured to retrieve the display configuration data into the random access memory when receiving a display control signal and to retrieve the optical compensation data into the random access memory when receiving a calibration control signal.

4. The system on chip according to claim 3 , wherein the non-volatile memory comprises a first storage area and a second storage area, and
the display configuration data is stored in the first storage area, and the image sampling data and the display configuration data are stored in the first storage area and the second storage area.

5. The system on chip according to claim 1 , wherein the control signal comprises a display control signal and a calibration control signal, and
the micro-processing unit is further configured to receive one of the display control signal and the calibration control signal, and output a display instruction in response to the display control signal or output a calibration instruction in response to the calibration control signal.

6. The system on chip according to claim 5 , wherein the display control signal and the calibration control signal are mutually exclusive control signals.

7. The system on chip according to claim 1 , wherein the display calibration unit is further configured to receive the image sampling data and generate the optical compensation data based on the image sampling data and a preset compensation algorithm.

8. The system on chip according to claim 1 , further comprising a compensated data extraction unit connected to the micro-processing unit,
wherein the compensated data extraction unit is configured to:
receive initial picture data in response to the display instruction,
perform the picture compensation operation based on the initial picture data, the display configuration data, and the optical compensation data to generate compensated picture data, and
send the compensated picture data to the active light-emitting display panel for display.

9. The system on chip according to claim 8 , wherein the image processing unit comprises an image quality enhancement unit connected to the micro-processing unit, and
the image quality enhancement unit is configured to superimpose image quality enhancement data to the compensated picture data in response to a received image quality enhancement trigger instruction.

10. The system on chip according to claim 9 , wherein the control signal comprises a display control signal and a calibration control signal, and the micro-processing unit comprises:
a first sub-micro-processing unit connected to the shared storage unit, the display calibration unit, and the compensated data extraction unit, wherein the first sub-micro-processing unit is configured to receive the calibration control signal and send the calibration instruction to trigger the enablement of the shared storage unit in response to the calibration control signal; and
a second sub-micro-processing unit connected to the shared storage unit and the image quality enhancement unit, wherein the second sub-micro-processing unit is configured to receive the display control signal and send the display instruction to trigger the enablement of the shared storage unit in response to the display control signal.

11. The system on chip according to claim 9 , further comprising a data output unit connected to the image quality enhancement unit and the compensated data extraction unit,
wherein the data output unit is configured to realize communication and transmission between the image quality enhancement unit and the active light-emitting display panel by using a display signal interface protocol.

12. The system on chip according to claim 11 , wherein the display signal interface protocol comprises any one of a Point to Point (P2P) protocol, a V-by-One (VBO) protocol, an Embedded DisplayPort (eDP) protocol, or a Low-Voltage Differential Signaling (LVDS).

13. A display device comprising a system on chip and an active light-emitting display panel connected to each other, wherein the system on chip comprises:
a shared storage unit configured to store image sampling data, display configuration data, and optical compensation data;
a micro-processing unit connected to the shared storage unit, wherein the micro-processing unit is configured to receive a control signal and output a control instruction in response to the control signal to trigger enablement of the shared storage unit, the control instruction comprising one of a display instruction and a calibration instruction;
a display calibration unit connected to the micro-processing unit, wherein the display calibration unit is configured to, in response to the calibration instruction, obtain the image sampling data in the shared storage unit to perform a compensation computation operation and generate the optical compensation data; and
an image processing unit connected to the micro-processing unit, wherein the image processing unit is configured to, in response to the display instruction, obtain the display configuration data and the optical compensation data in the shared storage unit to perform a picture compensation operation.

14. The display device according to claim 13 , wherein the shared storage unit comprises at least one random access memory connected to the micro-processing unit, and
the micro-processing unit is configured to release the random access memory when the display calibration unit finishes the compensation computation operation or when the image processing unit finishes the picture compensation operation.

15. The display device according to claim 14 , wherein the shared storage unit f

Assignees

• Shenzhen Tcl New Tech Co Ltd

Inventors

• Feng Lin
• Chen Yikai

Classifications

• G06T1/60

  Memory management · CPC title

• G06F15/167

  using a common memory, e.g. mailbox · CPC title

• G09G3/3225 Primary

  using an active matrix · CPC title

• G06T7/0002

  Inspection of images, e.g. flaw detection · CPC title

• G06T2207/30168

  Image quality inspection · CPC title