Efficient signaling scheme for high-speed ultra short reach interfaces

Patent metadata

Field	Value
Publication number	US-12248418-B2
Application number	US-202318512744-A
Country	US
Kind code	B2
Filing date	Nov 17, 2023
Priority date	Mar 28, 2016
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

A multi-chip package includes first and second groups of integrated circuit (IC) chips and a transfer IC chip disposed in the multi-chip package. The transfer IC chip is communicatively interposed between the first and second groups of IC chips and is configured to transfer signals from at least a first IC chip of the first group of IC chips to at least a second IC chip of the second group of IC chips or an output interface. The output interface is configured to output first data from the multi-chip package. A first set of ultra-short reach (USR) signaling links connects the first group of IC chips to the transfer IC chip. A second set of USR signaling links connects the second group of IC chips to the transfer IC chip. Each of the USR signaling links comprises a trace length of less than one inch.

First claim

We claim:

1. A multi-chip package, comprising:
a first group of integrated circuit (IC) chips disposed in the multi-chip package;
a second group of IC chips disposed in the multi-chip package;
a transfer IC chip disposed in the multi-chip package, the transfer IC chip communicatively interposed between the first group of IC chips and the second group of IC chips, the transfer IC chip configured to transfer signals from at least a first IC chip of the first group of IC chips to at least a second IC chip of the second group of IC chips or an output interface, the output interface configured to output first data from the multi-chip package;
a first set of ultra-short reach (USR) signaling links connecting the first group of IC chips to the transfer IC chip; and
a second set of USR signaling links connecting the second group of IC chips to the transfer IC chip,
each of the USR signaling links comprises a trace length of less than one inch.

2. The multi-chip package of claim 1 , wherein:
each of the USR signaling links comprises a simultaneously bidirectional signaling link.

3. The multi-chip package of claim 1 , further comprising a common package substrate, wherein at least one IC chip of the first group of IC chips, at least one IC chip of the second group of IC chips, and the transfer IC chip are mounted to the common package substrate in a planar configuration.

4. The multi-chip package of claim 1 , wherein the transfer IC chip is configured as a repeater.

5. The multi-chip package of claim 1 , wherein the transfer IC chip includes switching circuitry to selectively forward the signals from the at least the first IC chip of the first group of IC chips to the at least the second IC chip of the second group of IC chips or the output interface.

6. A semiconductor device package, comprising:
a first group of IC chips disposed in the semiconductor device package and including a first integrated circuit (IC) chip to transmit first data off the first IC chip; and
a transfer IC chip disposed in the semiconductor device package, the transfer IC chip to receive the first data from the first IC chip via at least one first bidirectional link, the transfer IC chip including switching circuitry to selectively forward the first data to one of a first output interface or a second output interface, the first output interface communicatively coupled to a third IC chip of a second group of IC chips via at least one second bidirectional link, the second group of IC chips being disposed in the semiconductor device package, the second output interface configured to output the first data from the semiconductor device package;
wherein the at least one first bidirectional link further comprises a first set of ultra-short reach (USR) bidirectional signaling links connecting the first group of IC chips to the transfer IC chip;
wherein the at least one second bidirectional link further comprises a second set of USR bidirectional signaling links connecting the second group of IC chips to the transfer IC chip; and
wherein each of the USR bidirectional signaling links comprises a trace length of less than one inch.

7. The semiconductor device package of claim 6 , wherein the transfer IC chip further comprises on-chip conductors to supply the first data on-chip to the switching circuitry.

8. The semiconductor device package of claim 6 , wherein the second output interface comprises a serial data port for communicating with a serial link.

9. The semiconductor device package of claim 6 , wherein each of the USR bidirectional signaling links comprises a simultaneously bidirectional signaling link.

10. The semiconductor device package of claim 6 , further comprising a common package substrate, wherein at least one IC chip of the first group of IC chips, at least one IC chip of the second group of IC chips, and the transfer IC chip are mounted to the common package substrate in a planar configuration.

11. A semiconductor device, comprising:
a chip package comprising a first group of IC chips and a second group of IC chips; and
a first integrated circuit (IC) chip disposed in the chip package, the first IC chip having an input interface to receive first data from the first group of IC chips via at least one first bidirectional link, the first IC chip including switching circuitry to selectively forward the first data to one of a first output interface or a second output interface, the first output interface for coupling to the second group of IC chips via at least one second bidirectional link, the second output interface configured to output the first data from the chip package;
wherein the at least one first bidirectional link further comprises a first set of ultra-short reach (USR) bidirectional signaling links connecting the first group of IC chips to the first IC chip;
wherein the at least one second bidirectional link further comprises a second set of USR bidirectional signaling links connecting the second group of IC chips to the first IC chip; and
wherein each of the USR bidirectional signaling links comprises a trace length of less than one inch.

12. The semiconductor device of claim 11 , wherein the first IC chip includes on-chip conductors to supply the first data on-chip from the input interface to the switching circuitry.

13. The semiconductor device of claim 11 , wherein the first IC chip is configured as a repeater.

14. The semiconductor device of claim 11 , wherein the second output interface comprises a serial data port for communicating with a serial link.

15. The semiconductor device of claim 11 , wherein the chip package comprises a common package substrate, and wherein the first IC chip is configured for mounting to the common package substrate in a planar orientation with the first group of IC chips and the second group of IC chips.

Assignees

• Marvell Asia Pte Ltd

Inventors

• Farjadrad Ramin
• Langner Paul

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/00

  Package configurations · CPC title

• H04L25/20

  Repeater circuits; Relay circuits · CPC title

• H04L7/0091

  Transmitter details · CPC title

• G06F13/4068

  Electrical coupling · CPC title