Address boundary functions for physical and localized addresses

Patent metadata

Field	Value
Publication number	US-12248405-B2
Application number	US-202318474411-A
Country	US
Kind code	B2
Filing date	Sep 26, 2023
Priority date	Feb 1, 2023
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

An integrated circuit for translating and reverse-translating the address included in a memory request is disclosed. The integrated circuit may first comprise a processor, a first boundary function, a second boundary function, and a component device. The processor is configured to transmit a memory request to a target module over a bus of the integrated circuit. The memory request requests access to one or more memory mapped resources and the memory request includes a physical address. The first boundary function is configured to translate the physical address to a relative address which operates in or applies to a different address space than an address space that the physical address operates in or applies to. The second boundary function is configured to translate the relative address to the physical address. The device is configured utilize the physical address transmitted by the second boundary function.

First claim

What is claimed is:

1. An integrated circuit for executing instructions comprising:
a processor configured to transmit a memory request to a target module over a bus of the integrated circuit, wherein the memory request requests access to one or more memory mapped resources, wherein the memory request includes a physical address;
a first boundary function configured to translate the physical address to a relative address, wherein the relative address operates in or applies to a different address space than an address space that the physical address operates in or applies to, wherein the first boundary function is programmed to identify the physical address, subtract a physical base address from the physical address, and add a relative base address to a subtracted physical address to generate the relative address;
a second boundary function configured to translate the relative address to the physical address, wherein the second boundary function is programmed to identify the relative address, subtract the base relative address, and add the physical base address to a subtracted relative address to generate the physical address; and
a device configured to utilize the physical address transmitted by the second boundary function.

2. The integrated circuit of claim 1 , wherein the second boundary function is located within the device.

3. The integrated circuit of claim 1 , wherein the second boundary function is located within the bus.

4. The integrated circuit of claim 1 , wherein the device is a security device comprising:
a data store configured to store a permission identifier,
a permission identifier marker circuitry configured to tag the memory requests with the permission identifier; and
a permission identifier checker circuitry configured to check the memory request for the one or more memory mapped resources that are received via the bus that have been tagged with the permission identifier to determine whether to allow or reject access based on the tagged permission identifier and the physical address of the memory request.

5. The integrated circuit of claim 1 , wherein:
the physical base address and the relative base address are equivalent such that either one of the physical base address or the relative base address is treated as a base address;
the first boundary function is programmed to identify the physical address and subtract a base address from the physical address to generate the relative address; and
the second boundary function is programmed to identify the relative address and add the base address to generate the physical address.

6. The integrated circuit of claim 1 , wherein the first boundary function and the second boundary function both include at least three fields necessary for address translation, the at least three fields comprising a physical base address field, a length of address range field, and a relative base address field.

7. The integrated circuit of claim 6 , wherein the second boundary function includes a blank register, and values of the fields including the length of address field and the relative base address field are populated based on a parameter, wherein the parameter is determined based on a travel path of the memory request and whether the memory request crossed the boundary function.

8. The integrated circuit of claim 7 , wherein the second boundary function comprises a hardware hardcoded with the values of the fields including the length of address field and the relative base address field based on the parameter, wherein the hardware is configured to identify the relative address.

9. The integrated circuit of claim 1 , wherein the second boundary function comprises a hardware hardcoded in a way that the hardware is configured to identify the relative address.

10. A method comprising:
transmitting, by a processor core, a memory request for access to one or more memory mapped resources onto a bus of a circuit, wherein the memory request includes a physical address of the one or more memory mapped resources;
translating, by a first boundary function, the physical address to a relative address, wherein the relative address operates in or applies to a different address space than an address space that the physical address operates in or applies to;
translating, by a second boundary function, the relative address to the physical address, wherein the second boundary function comprises a register programmed with values from one or more boundary functions located between the processor core and the one or more memory mapped resources; and
transmitting, by the second boundary function, the memory request to a device configured to utilize the physical address received from the second boundary function.

11. The method of claim 10 , wherein the second boundary function is located within the device.

12. The method of claim 11 , wherein the device is a security device, the security device comprising:
a first data store configured to store a first permission identifier,
a permission identifier marker circuitry configured to tag the memory requests with the first permission identifier; and
a permission identifier checker circuitry configured to check the memory requests for the one or more memory mapped resources that are received via the bus that have been tagged with a permission identifier to determine whether to allow or reject access based on the tagged permission identifier and the physical address.

13. The method of claim 12 , wherein the second boundary function is located within the bus of the circuit.

14. The method of claim 13 , wherein the first boundary function is programmed to identify the physical address and subtract a base address to generate the relative address, and the second boundary function is programmed to identify the relative address and add the base address to generate the physical address.

15. The method of claim 14 , wherein the second boundary function comprises a hardware hardcoded in a way that the hardware is configured to identify the relative address.

16. The method of claim 15 , wherein:
the first boundary function is programmed to identify the physical address, subtract a physical base address from the physical address, and add a relative base address to a subtracted physical address to generate the relative address; and
the second boundary function is programmed to identify the relative address, subtract the base relative address, and add the physical base address to a subtracted relative address to generate the physical address.

17. The method of claim 10 , wherein the first boundary function and the second boundary function both include at least three fields necessary for address translation, the at least three fields comprising a physical base address field, a length of address range field, and a relative base address field.

18. An integrated circuit for executing instructions comprising:
a processor core configured to execute instructions and generate a memory request for access to memory-mapped resource;
a bus configured to communicate the memory request for access to memory-mapped resource, wherein the memory request is transmitted from the processor core and the bus comprises a boundary function configured to convert a relative address of the memory request to a physical address of the memory request; and
a security module configured to permit access to the memory mapped resource based on the physical address.

19. The integrated circuit of claim 18 , wherein the security module comprises:
a first data store configured to store a first permiss

Assignees

• Sifive Inc

Inventors

• Liberty Dean
• Adler Robert P
• Cook Henry
• Sensaoui Abderrahmane
• Peresse Perrine

Classifications

• G06F21/79

  in semiconductor storage media, e.g. directly-addressable memories · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F2212/1052

  Security improvement · CPC title

• G06F12/1441

  for a range · CPC title

• G06F12/10 Primary

  Address translation · CPC title