Interconnect networks using microLED-based optical links

Patent metadata

Field	Value
Publication number	US-12244355-B2
Application number	US-202318495689-A
Country	US
Kind code	B2
Filing date	Oct 26, 2023
Priority date	Apr 13, 2020
Publication date	Mar 4, 2025
Grant date	Mar 4, 2025

Abstract

Integrated circuit chips may be optically interconnected using microLEDs. Some interconnections may be vertically-launched parallel optical links. Some interconnections may be planar-launched parallel optical links.

First claim

What is claimed is:

1. Optical interconnections for integrated circuit chips, comprising:
a plurality of substrates, each substrate having holes traversing through a body of the substrate from a first side to a second side of the substrate;
a plurality of integrated circuit chips mounted to the plurality of substrates;
a plurality of optoelectronic devices including microLEDs and photodetectors on the plurality of integrated circuit chips, the plurality of optoelectronic devices being within the holes of the plurality of substrates;
a plurality of vertically launched parallel optical links (VLPOLs) optically fitting within the holes of the plurality of substrates and interconnecting at least some of the plurality of optoelectronic devices; and
a plurality of planar launched parallel optical links (PLPOLs) optically interconnecting at least some of the plurality of optoelectronic devices.

2. The optical interconnections for integrated circuit chips of claim 1 , wherein at least some of the substrates define a plane, at least some of the substrates defining different planes.

3. The optical interconnections for integrated circuit chips of claim 1 , wherein the different planes are parallel to one another.

4. The optical interconnections for integrated circuit chips of claim 3 , wherein at least some of the substrates define a same plane.

5. The optical interconnections for integrated circuit chips of claim 4 , wherein PLPOLs interconnect integrated circuit chips on substrates defining the same plane and VLPOLs interconnect integrated circuit chips on substrates defining different planes.

6. The optical interconnections for integrated circuit chips of claim 1 , wherein the different planes are not parallel to one another.

7. The optical interconnections for integrated circuit chips of claim 6 , wherein the substrates are on surfaces of a bulk optical medium.

8. The optical interconnections for integrated circuit chips of claim 7 , wherein the bulk optical medium includes optical components.

9. The optical interconnections for integrated circuit chips of claim 1 , wherein the substrates define a same plane.

10. The optical interconnections for integrated circuit chips of claim 9 , wherein the PLPOLs and VLPOLs have a partial irregular hypercube interconnect topology.

11. The optical interconnections for integrated circuit chips of claim 1 , wherein the VLPOLs and PLPOLs are flexible multicore fibers.

12. The optical interconnections for integrated circuit chips of claim 1 , wherein the VLPOLs and PLPOLs are multicore waveguides.

13. The optical interconnections for integrated circuit chips of claim 1 , wherein the microLEDs of the plurality of optoelectronic devices each have an emitting region of less than or equal to 20 μm×20 μm.

14. The optical interconnections for integrated circuit chips of claim 1 , wherein the microLEDs of the plurality of optoelectronic devices each have an end with a lens formed on said end.

Assignees

• Avicenatech Corp

Inventors

• Kalman Robert
• Pezeshki Bardia
• Tselikov Alexander
• Danesh Cameron

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10H20/814

  having reflecting means, e.g. semiconductor Bragg reflectors · CPC title

• H10H20/042

  Superluminescent diodes · CPC title

• H04B10/25

  Arrangements specific to fibre transmission · CPC title

• H04J14/0217

  Multi-degree architectures, e.g. having a connection degree greater than two · CPC title