Method and apparatus for improving write uniformity in a memory device

Patent metadata

Field	Value
Publication number	US-12243590-B2
Application number	US-202117528892-A
Country	US
Kind code	B2
Filing date	Nov 17, 2021
Priority date	Nov 17, 2021
Publication date	Mar 4, 2025
Grant date	Mar 4, 2025

Abstract

In one embodiment, an apparatus comprises a memory comprising a group of memory cells coupled to a wordline; and a controller configured to skip programming of one or more pages of the group of memory cells responsive to a sequential write operation; and program the one or more pages of the group of memory cells responsive to one or more random write commands.

First claim

What is claimed is:

1. An apparatus comprising:
a memory comprising a group of memory cells coupled to a wordline; and
a controller configured to:
program one or more lower pages of the group of memory cells responsive to a sequential write operation;
skip programming of one or more upper pages of the group of memory cells responsive to the sequential write operation; and
program the one or more upper pages of the group of memory cells responsive to one or more random write commands.

2. The apparatus of claim 1 , wherein a write uniformity of the sequential write operation is improved by the skipping of the programming of the one or more upper pages of the group of memory cells responsive to the sequential write operation.

3. The apparatus of claim 2 , the controller to skip programming of one or more pages of a second group of memory cells coupled to a second wordline responsive to the sequential write operation, wherein the write uniformity of the sequential write operation is further improved by the skipping of the programming of the one or more pages of the second group of memory cells.

4. The apparatus of claim 1 , wherein the one or more upper pages that are skipped comprise a top page (TP) and an extra page (XP).

5. The apparatus of claim 1 , wherein the controller is further to adjust one or more voltages to compensate for the skipped programming of the one or more upper pages.

6. The apparatus of claim 1 , wherein the one or more lower pages of the group of memory cells that are programmed comprise a lower page (LP) and an upper page (UP).

7. The apparatus of claim 1 , the controller to apply an offset for a read operation responsive to a determination that the programming of the one or more upper pages was skipped.

8. The apparatus of claim 1 , the controller to apply an offset for a program verify operation responsive to a determination that the programming of the one or more upper pages was skipped.

9. The apparatus of claim 1 , further comprising skipping programming of one or more upper pages of a second group of memory cells coupled to the wordline responsive to the sequential write operation, wherein the group of memory cells are part of a first subblock of the memory and the second group of memory cells are part of a second subblock of the memory.

10. The apparatus of claim 1 , wherein the apparatus comprises a solid state drive.

11. The apparatus of claim 1 , wherein the apparatus comprises a dual in-line memory module.

12. A method comprising:
detecting a sequential write operation;
skipping programming of one or more upper pages of a group of memory cells coupled to a wordline responsive to the detection of the sequential write operation;
programming one or more lower pages of the group of memory cells responsive to the detection of the sequential write operation; and
programming the one or more upper pages of the group of memory cells responsive to one or more random write commands.

13. The method of claim 12 , wherein a write uniformity of the sequential write operation is improved by the skipping of the programming of the one or more upper pages of the group of memory cells responsive to the sequential write operation.

14. The method of claim 12 , further comprising adjusting one or more voltages to compensate for the skipped programming of the one or more upper pages.

15. The method of claim 12 , wherein the one or more upper pages that are skipped comprise a top page (TP) and an extra page (XP).

16. A system comprising:
at least one memory chip comprising a group of memory cells coupled to a wordline; and
a storage device controller coupled to the at least one memory chip, the storage device controller to:
detect a sequential write operation;
skip programming of one or more upper pages of the group of memory cells responsive to the detection of the sequential write operation;
program one or more lower pages of the group of memory cells responsive to the detection of the sequential write operation; and
program the one or more pages of the group of memory cells responsive to one or more random write commands.

17. The system of claim 16 , further comprising a processor to execute an instruction requesting the sequential write operation and to send one or more requests for the sequential write operation to the storage device controller.

18. The system of claim 17 , further comprising one or more of: a battery communicatively coupled to the processor, a display communicatively coupled to the processor, or a network interface communicatively coupled to the processor.

19. The system of claim 16 , wherein a write uniformity of the sequential write operation is improved by the skipping of the programming of the one or more upper pages of the group of memory cells responsive to the detection of the sequential write operation.

20. The system of claim 16 , wherein a programming time for an equivalent number of pages is longer for the group of memory cells coupled to the wordline than for a second group of memory cells coupled to a second wordline adjacent to the wordline the storage device controller to request the programming of one or more pages of the group of memory cells responsive to the sequential write operation.

Assignees

• Intel Corp

Inventors

• Rajwade Shantanu R
• Mion Christian
• Kalavade Pranav
• Shenoy Rohit S
• Sun Xin
• Gaewsky Kristopher

Classifications

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G11C11/56

  using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency · CPC title