Method and apparatus for protecting lower page data during programming in NAND flash

Patent metadata

Field	Value
Publication number	US-9703494-B1
Application number	US-201615276080-A
Country	US
Kind code	B1
Filing date	Sep 26, 2016
Priority date	Sep 26, 2016
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to store a first page of data in a plurality of cells of the NAND flash memory in a first programming pass; and preserve the readability of the first page of data in the plurality of cells during a subsequent programming pass comprising a plurality of program loops, at least one of the plurality of program loops to comprise application of a first voltage to a first group of cells of the plurality of cells and application of a second voltage to a second group of cells of the plurality of cells, wherein the first group comprises cells that were not programmed in the first programming pass and the second group comprises cells that were programmed in the first programming pass.

First claim

What is claimed is:

1. An apparatus comprising:
a storage device comprising a NAND flash memory, the storage device to:
store a first page of data in a plurality of cells of the NAND flash memory in a first programming pass; and
preserve the readability of the first page of data in the plurality of cells during a subsequent programming pass comprising a plurality of program loops, at least one of the plurality of program loops to comprise application of a first voltage to a first group of cells of the plurality of cells and application of a second voltage to a second group of cells of the plurality of cells, wherein the first group comprises cells that were not programmed in the first programming pass and the second group comprises cells that were programmed in the first programming pass.

2. The apparatus of claim 1 , wherein the storage device is further to apply the first voltage to control gates of the first group of cells and apply the second voltage to control gates of the second group of cells.

3. The apparatus of claim 1 , wherein the storage device is further to step up the first voltage and the second voltage by an equal amount between program loops of the plurality of program loops.

4. The apparatus of claim 1 , wherein the storage device is further to apply the first voltage to the channels of the first group of cells and the second voltage to the channels of the second group of cells.

5. The apparatus of claim 1 , wherein the second group of cells comprises at least one cell that, after the first programming pass is completed and before the subsequent programming pass has started, has a threshold voltage that is lower than the threshold voltage of at least one cell of the first group of cells after the subsequent programming pass is completed.

6. The apparatus of claim 1 , wherein the storage device is further to preserve the readability of the first page of data in the plurality of cells during the subsequent programming pass by performing at least one program loop in which an effective program voltage is applied to cells of the second group, but an effective program voltage is not applied to cells of the first group.

7. The apparatus of claim 1 , wherein the storage device is further to apply the second voltage to the second group of cells prior to application of the first voltage to the first group of cells during a program loop of the subsequent programming pass.

8. The apparatus of claim 1 , wherein the storage device is further to apply the first voltage and the second voltage to a wordline coupled to the plurality of cells.

9. The apparatus of claim 1 , wherein the storage device is further to:
store a second page of data in the plurality of cells of the NAND flash memory in the first programming pass; and
preserve the readability of the second page of data in the plurality of cells during the subsequent programming pass.

10. The apparatus of claim 1 , wherein the storage device is further to program two additional pages of data in the plurality of cells during the subsequent programming pass.

11. The apparatus of claim 1 , wherein the storage device is further to read the first page of data after a power loss has interrupted the subsequent programming pass.

12. The apparatus of claim 11 , wherein the storage device is further to read the first page using a read voltage that is different from a read voltage that would have been used if the subsequent programming pass had completed.

13. A method comprising:
storing a first page of data in a plurality of cells of a NAND flash memory in a first programming pass; and
preserving the readability of the first page of data in the plurality of cells during a subsequent programming pass comprising a plurality of program loops, at least one of the plurality of program loops to comprise application of a first voltage to a first group of cells of the plurality of cells and application of a second voltage to a second group of cells of the plurality of cells, wherein the first group comprises cells that were not programmed in the first programming pass and the second group comprises cells that were programmed in the first programming pass.

14. The method of claim 13 , further comprising stepping up the first voltage and the second voltage by an equal amount between program loops of the plurality of program loops.

15. The method of claim 13 , wherein the first voltage and the second voltage are applied to a wordline coupled to the plurality of cells.

16. The method of claim 13 , further comprising reading the first page of data after a power loss has interrupted the subsequent programming pass.

17. A system comprising:
a processor to send a write request to a storage device; and
a storage device comprising:
a NAND flash memory; and
a storage device controller to:
store a first page of data identified by the write request in a plurality of cells of the NAND flash memory in a first programming pass; and
preserve the readability of the first page of data in the plurality of cells during a subsequent programming pass comprising a plurality of program loops, at least one of the plurality of program loops to comprise application of a first voltage to a first group of cells of the plurality of cells and application of a second voltage to a second group of cells of the plurality of cells, wherein the first group comprises cells that were not programmed in the first programming pass and the second group comprises cells that were programmed in the first programming pass.

18. The system of claim 17 , wherein the first voltage and the second voltage are stepped up by an equal amount between program loops of the plurality of program loops.

19. The system of claim 17 , wherein the storage device controller is further to read the first page of data after a power loss has interrupted the subsequent programming pass.

20. The system of claim 17 , further comprising one or more of: a battery communicatively coupled to the processor, a display communicatively coupled to the processor, or a network interface communicatively coupled to the processor.

Assignees

• Intel Corp

Inventors

• Rajwade Shantanu R
• Kalavade Pranav

Classifications

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/3459 Primary

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title