Reconfigurable channel interfaces for memory devices

Patent metadata

Field	Value
Publication number	US-12242408-B2
Application number	US-202217719316-A
Country	US
Kind code	B2
Filing date	Apr 12, 2022
Priority date	May 31, 2019
Publication date	Mar 4, 2025
Grant date	Mar 4, 2025

Abstract

Methods, systems, and devices for reconfigurable channel interfaces for memory devices are described. A memory device may be split into multiple logical channels, where each logical channel is associated with a memory array and a command/address (CA) interface. In some cases, the memory device may configure a first CA interface associated with a first channel to forward commands to a first memory array associated with the first channel and a second memory array associated with a second channel. The configuring may include isolating a second CA interface associated with the second channel from the second array and coupling the first CA interface with the second memory array.

First claim

What is claimed is:

1. A method, comprising:
deactivating a first command/address (CA) interface associated with a first memory array of a plurality of memory arrays;
coupling a second CA interface with the first memory array based at least in part on deactivating the first CA interface;
receiving, at the second CA interface over a control channel, a write command for the first memory array and a second memory array of the plurality of memory arrays coupled with the second CA interface, each memory array of the plurality of memory arrays coupled with a respective data channel of a plurality of data channels;
forwarding, by the second CA interface based at least in part on coupling the second CA interface with the first memory array, the write command to the first memory array and the second memory array;
receiving, over a first data channel of the plurality of data channels that is coupled with the first memory array, a first set of data based at least in part on the write command;
receiving, over a second data channel of the plurality of data channels that is coupled with the second memory array, a second set of data based at least in part on the write command; and
writing the first set of data to the first memory array and the second set of data to the second memory array based at least in part on receiving the first set of data and the second set of data.

2. The method of claim 1 , wherein:
writing the first set of data to the first memory array occurs within a first time period;
writing the second set of data to the second memory array occurs within a second time period; and
the first time period and the second time period at least partially overlap.

3. The method of claim 1 , wherein:
receiving the first set of data over the first data channel occurs within a first time period;
receiving the second set of data over the second data channel occurs within a second time period; and
the first time period and the second time period at least partially overlap.

4. The method of claim 1 , further comprising:
transmitting, by the second CA interface, the write command over a first internal channel coupled with the second CA interface and the first memory array, wherein forwarding the write command to the first memory array is based at least in part on transmitting the write command over the first internal channel; and
transmitting, by the second CA interface, the write command over a second internal channel coupled with the second CA interface and the second memory array, wherein forwarding the write command to the second memory array is based at least in part on transmitting the write command over the second internal channel.

5. The method of claim 1 , wherein the write command, the first set of data, and the second set of data are received from a host device coupled with the control channel and the plurality of data channels.

6. The method of claim 1 , further comprising:
decoding, by a command decoder of the second CA interface, the write command based at least in part on receiving the write command; and
identifying that the write command is for the first memory array and the second memory array based at least in part on decoding the write command.

7. The method of claim 1 , further comprising:
receiving, at the first CA interface, a command indicating a configuration of a plurality of CA interfaces including the first CA interface; and
deactivating the first CA interface that is coupled with the first memory array based at least in part on receiving the command, wherein receiving the write command for the first memory array and the second memory array is based at least in part on deactivating the first CA interface.

8. The method of claim 1 , wherein a sum of a first quantity of bytes included in the first set of data and a second quantity of bytes included in the second set of data is equal to a total quantity of bytes indicated via the write command based at least in part on a configuration of the control channel and the plurality of data channels.

9. A method, comprising:
deactivating a first command/address (CA) interface associated with a first memory array of a plurality of memory arrays;
coupling a second CA interface with the first memory array based at least in part on deactivating the first CA interface;
receiving, at the second CA interface, a read command for two or more memory arrays of the plurality of memory arrays, each memory array of the plurality of memory arrays coupled with a respective data channel of a plurality of data channels;
retrieving, by the second CA interface based at least in part on coupling the second CA interface with the first memory array, a first set of data from the first memory array of the two or more memory arrays and a second set of data from a second memory array of the two or more memory arrays based at least in part on the read command;
transmitting the first set of data over a first data channel of the plurality of data channels that is coupled with the first memory array based at least in part on retrieving the first set of data from the first memory array; and
transmitting the second set of data over a second data channel of the plurality of data channels that is coupled with the second memory array based at least in part on retrieving the second set of data from the second memory array.

10. The method of claim 9 , wherein:
transmitting the first set of data over the first data channel occurs within a first time period;
transmitting the second set of data over the second data channel occurs within a second time period; and
the first time period and the second time period at least partially overlap.

11. The method of claim 9 , further comprising:
forwarding, by the second CA interface, the read command to the first memory array over a first internal channel coupled with the second CA interface and the first memory array; and
forwarding, by the second CA interface, the read command to the second memory array over a second internal channel coupled with the second CA interface and the second memory array.

12. The method of claim 9 , wherein:
the read command is received from a host device via a control channel coupled with the second CA interface;
the first set of data is transmitted to the host device via the first data channel; and
the second set of data is transmitted to the host device via the second data channel.

13. The method of claim 9 , further comprising:
decoding, by a command decoder of the second CA interface, the read command based at least in part on receiving the read command; and
identifying that the read command is for the first memory array and the second memory array based at least in part on decoding the read command.

14. The method of claim 9 , further comprising:
receiving, at the first CA interface, a command indicating a configuration of a plurality of CA interfaces comprising the first CA interface; and
deactivating the first CA interface that is coupled with the first memory array based at least in part on receiving the command, wherein receiving the read command for the first memory array and the second memory array is based at least in part on deactivating the first CA interface.

15. The method of claim 9 , wherein a total quantity of bytes included in the first set of data and the second set of data is the same as a quantity of bytes of data requested via the read command based at least in part on a configuration of a control channel coupled with the second CA interface and the plurality of data channels.

16. A method, comprising:
receiving, at a first command/address

Assignees

• Micron Technology Inc

Inventors

• Richter Michael Dieter

Classifications

• G06F13/4027 Primary

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C7/1045

  Read-write mode select circuits · CPC title

• G11C11/4096 Primary

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title