Display panel and display device

Patent metadata

Field	Value
Publication number	US-12238976-B2
Application number	US-202418594819-A
Country	US
Kind code	B2
Filing date	Mar 4, 2024
Priority date	Aug 17, 2020
Publication date	Feb 25, 2025
Grant date	Feb 25, 2025

Abstract

The disclosure provides a display panel and a display device. The display panel includes: a base substrate, a transistor array layer, a pixel defining layer, touch electrodes. The area of opening region of first color sub-pixel is smaller than that of opening region of third color sub-pixel, the area of opening region of second color sub-pixel is smaller than that of opening region of third color sub-pixel. An orthogonal projection of second capacitor in first color sub-pixel and an orthogonal projection of touch electrodes have a first auxiliary overlap area, an orthogonal projection of second capacitor in second color sub-pixel and orthogonal projection of the touch electrodes have a second auxiliary overlap area, an orthogonal projection of second capacitor in third color sub-pixel and orthogonal projection of touch electrodes have a third auxiliary overlap area. The first and/or second auxiliary overlap area is larger than the third auxiliary overlap area.

First claim

What is claimed is:

1. A display panel, comprising:
a base substrate;
a transistor array layer, located on the base substrate;
a pixel defining layer, located on a side of the transistor array layer facing away from the base substrate; and
touch electrodes, located on a side of the pixel defining layer facing away from the base substrate; wherein
the base substrate has a display region comprising a plurality of sub-pixels; the sub-pixels comprise pixel circuits and light emitting elements; the pixel circuits comprise gate line patterns, data line patterns, and power supply signal line patterns;
an orthogonal projection of at least part of the touch electrodes on the base substrate is a grid;
the plurality of sub-pixels further comprise a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel; an area of an opening region of the first color sub-pixel is smaller than an area of an opening region of the third color sub-pixel, and an area of an opening region of the second color sub-pixel is smaller than the area of the opening region of the third color sub-pixel;
wherein the pixel circuits further comprise first capacitors;
an orthogonal projection of a first capacitor in the first color sub-pixel on the base substrate overlaps with the orthogonal projection of the touch electrodes on the base substrate at a first storage overlap area;
an orthogonal projection of a first capacitor in the second color sub-pixel on the base substrate overlaps with the orthogonal projection of the touch electrodes on the base substrate at a second storage overlap area;
an orthogonal projection of a first capacitor in the third color sub-pixel on the base substrate overlaps with the orthogonal projection of the touch electrodes on the base substrate at a third storage overlap area; and
at least one of the first storage overlap area and the second storage overlap area is larger than the third storage overlap area.

2. The display panel according to claim 1 , wherein the transistor array layer comprises a plurality of capacitance-conductive portions, and the sub-pixels comprise corresponding capacitance-conductive portions; wherein, in each of the sub-pixels, there is an overlapping region between a capacitance-conductive portion and a data line pattern corresponding to the each of the sub-pixels and/or a power supply signal line pattern corresponding to the each of the sub-pixels; the capacitance-conductive portion is at least coupled to the power supply signal line pattern corresponding to the each of the sub-pixels or the data line pattern corresponding to the each of the sub-pixels;
the pixel defining layer comprises a plurality of opening regions, and the sub-pixels comprise corresponding opening regions;
an orthogonal projection of a capacitance-conductive portion in the first color sub-pixel on the base substrate overlaps with an orthogonal projection of the touch electrodes on the base substrate at a first auxiliary overlap area;
an orthogonal projection of a capacitance-conductive portion in the second color sub-pixel on the base substrate overlaps with the orthogonal projection of the touch electrodes on the base substrate at a second auxiliary overlap area;
an orthogonal projection of a capacitance-conductive portion in the third color sub-pixel on the base substrate overlaps with the orthogonal projection of the touch electrodes on the base substrate at a third auxiliary overlap area; and
at least one of the first auxiliary overlap area and the second auxiliary overlap area is larger than the third auxiliary overlap area.

3. The display panel according to claim 2 , wherein the first auxiliary overlap area is larger than the second auxiliary overlap area; or,
the first auxiliary overlap area is substantially equal to the second auxiliary overlap area; or,
the third auxiliary overlap area is substantially equal to the second auxiliary overlap area.

4. The display panel according to claim 2 , wherein the transistor array layer comprises:
a first conductive layer, located between the base substrate and the pixel defining layer; wherein the first conductive layer comprises a plurality of data line patterns and a plurality of power supply signal line patterns;
a first insulating layer, located between the base substrate and the first conductive layer; and
a second conductive layer, located between the base substrate and the first insulating layer, the second conductive layer comprises: a plurality of auxiliary conductive portions, the capacitance-conductive portions of the sub-pixels comprising the auxiliary conductive portions; wherein in each of the sub-pixels, an orthogonal projection of a first end of an auxiliary conductive portion on the base substrate has an overlapping region with an orthogonal projection of a power supply signal line pattern on the base substrate, and an orthogonal projection of a second end of the auxiliary conductive portion on the base substrate has an overlapping region with an orthogonal projection of a data line pattern on the base substrate; the auxiliary conductive portion is coupled to the power supply signal line pattern;
the first auxiliary overlap area comprises an overlap area between an orthogonal projection of the auxiliary conductive portion in the first color sub-pixel on the base substrate and the orthogonal projection of the touch electrodes on the base substrate;
the second auxiliary overlap area comprises an overlap area between an orthogonal projection of the auxiliary conductive portion in the second color sub-pixel on the base substrate and the orthogonal projection of the touch electrodes on the base substrate; and
the third auxiliary overlap area comprises an overlap area between an orthogonal projection of the auxiliary conductive portion in the third color sub-pixel on the base substrate and the orthogonal projection of the touch electrodes on the base substrate;
wherein the auxiliary conductive portion in the first color sub-pixel comprises a first auxiliary exposure portion, and an orthogonal projection of the first auxiliary exposure portion on the base substrate does not overlap with the orthogonal projections of the data line patterns and the power supply signal line patterns, respectively, on the base substrate; the first auxiliary overlap area comprises a first auxiliary sub-overlap area, and an overlapping region between the orthogonal projection of the first auxiliary exposure portion on the base substrate and the orthogonal projection of the touch electrodes on the base substrate comprises the first auxiliary sub-overlap area;
the auxiliary conductive portion in the second color sub-pixel comprises a second auxiliary exposure portion, and an orthogonal projection of the second auxiliary exposure portion on the base substrate does not overlap with the orthogonal projections of the data line patterns and the power supply signal line patterns, respectively, on the base substrate; the second auxiliary overlap area comprises a second auxiliary sub-overlap area, and an overlapping region between the orthogonal projection of the second auxiliary exposure portion on the base substrate and the orthogonal projection of the touch electrodes on the base substrate comprises the second auxiliary sub-overlap area;
the auxiliary conductive portion in the third color sub-pixel comprises a third auxiliary exposure portion, and an orthogonal projection of the third auxiliary exposure portion on the base substrate does not overlap with the orthogonal projections of the data line patterns and the power supply signal line patterns, respectively, on the base substrate; the third auxiliary overlap area comprises a third auxiliary sub-overlap area, and an overlapping region between the orthogonal projection of the third auxiliary exposure portion on the base substrate and the

Assignees

• Beijing Boe Technology Dev Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Xian Jianbo
• Xu Chen
• Li Pan
• Qiao Yong
• Wu Xinyin

Classifications

• H10K59/1216

  the pixel elements being capacitors · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10K59/353

  characterised by the geometrical arrangement of the RGB subpixels · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/40 Primary

  OLEDs integrated with touch screens · CPC title