Two transistor memory cell using stacked thin-film transistors

Patent metadata

Field	Value
Publication number	US-12238913-B2
Application number	US-202318161915-A
Country	US
Kind code	B2
Filing date	Jan 31, 2023
Priority date	Sep 17, 2018
Publication date	Feb 25, 2025
Grant date	Feb 25, 2025

Abstract

Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

First claim

The invention claimed is:

1. An integrated circuit (IC) device, comprising:
a support;
a first thin-film transistor (TFT) in a first layer over the support;
a second TFT in a second layer over the support, wherein the first layer is between the support and the second layer, and each of the first TFT and the second TFT includes a pair of a source electrode and a drain electrode; and
a via having a first end and an opposing second end, wherein the first end is directly electrically connected with a first electrode of the pair of the first TFT and the second end is directly electrically connected with a gate electrode of the second TFT.

2. The IC device according to claim 1 , wherein a gate electrode of the first TFT is directly connected to a write wordline.

3. The IC device according to claim 1 , wherein a second electrode of the pair of the first TFT is directly connected to a write bitline.

4. The IC device according to claim 1 , wherein a first electrode of the pair of the second TFT is directly connected to a read wordline.

5. The IC device according to claim 1 , wherein a second electrode of the pair of the second TFT is directly connected to a read bitline.

6. The IC device according to claim 1 , further comprising a capacitor having a capacitor electrode directly electrically connected to the first electrode of the pair of the first TFT, wherein the capacitor is closer to the support than the second TFT.

7. The IC device according to claim 1 , further comprising:
a capacitor comprising a first capacitor electrode, a second capacitor electrode, and a capacitor insulator between the first capacitor electrode and the second capacitor electrode; and
an insulator material around the capacitor,
wherein:
the insulator material includes an opening substantially perpendicular to the support,
the first capacitor electrode includes a first conductive material on sidewalls and a bottom of the opening,
the capacitor insulator includes a dielectric material on the first conductive material on the sidewalls and the bottom of the opening, and
the second capacitor electrode includes a second conductive material in the opening.

8. The IC device according to claim 7 , wherein the second conductive material is further away from the sidewalls of the opening.

9. The IC device according to claim 8 , wherein the first capacitor electrode is directly electrically connected to the first electrode of the pair of the first TFT.

10. The IC device according to claim 7 , wherein the first capacitor electrode is directly electrically connected to the first electrode of the pair of the first TFT.

11. The IC device according to claim 1 , wherein the second end is closer to a channel region of the first TFT than the gate electrode of the second TFT.

12. The IC device according to claim 11 , wherein the channel region of the first TFT is closer to the support than a channel region of the second TFT.

13. The IC device according to claim 1 , wherein the first end is closer to a channel region of the first TFT than the second end.

14. An integrated circuit (IC) device, comprising:
a device layer;
a memory cell over the device layer, the memory cell comprising a stack of a first transistor and a second transistor; and
a via,
wherein:
along a line perpendicular to the device layer in a cross-section along a plane perpendicular to the device layer, a channel region of the first transistor is between the device layer and a channel region of the second transistor,
a gate electrode of the second transistor is directly electrically connected to one end of the via, and
one electrode of a source electrode and a drain electrode of the first transistor is directly electrically connected to another end of the via.

15. The IC device according to claim 14 , wherein:
the memory cell is a first memory cell,
the IC device further includes a second memory cell comprising a stack of a third transistor and a fourth transistor,
a channel region of the third transistor is between the device layer and a channel region of the fourth transistor,
the first memory cell further includes a first capacitor connected to the one electrode of the source electrode and the drain electrode of the first transistor,
the second memory cell further includes a second capacitor connected to one electrode of a source electrode and a drain electrode of the third transistor, and
an individual one of the first capacitor and the second capacitor is further connected to a common conductive line parallel to the device layer.

16. The IC device according to claim 15 , wherein:
an individual one of the first capacitor and the second capacitor includes a first capacitor electrode, a second capacitor electrode, and an insulator between the first capacitor electrode and the second capacitor electrode,
the first capacitor is connected to the one electrode of the source electrode and the drain electrode of the first transistor by having the first capacitor electrode of the first capacitor being directly electrically connected with the one electrode of the source electrode and the drain electrode of the first transistor,
the second capacitor is connected to the one electrode of the source electrode and the drain electrode of the third transistor by having the first capacitor electrode of the second capacitor being directly electrically connected with the one electrode of the source electrode and the drain electrode of the third transistor, and
an individual one of the first capacitor and the second capacitor is further connected to the common conductive line by having the second capacitor electrode of an individual one of the first capacitor and the second capacitor being directly electrically connected with the common conductive line.

17. The IC device according to claim 15 , wherein a distance between the common conductive line and the channel region of the first transistor is smaller than a distance between the channel region of the second transistor and the channel region of the first transistor.

18. The IC device according to claim 14 , further comprising a capacitor having a capacitor electrode directly electrically connected to the one electrode of the source electrode and the drain electrode of the first transistor, wherein the capacitor is closer to the device layer than the second transistor.

19. The IC device according to claim 14 , wherein a gate electrode of the first transistor is directly electrically connected to a write wordline.

20. The IC device according to claim 14 , wherein another electrode of the source electrode and the drain electrode of the first transistor is directly electrically connected to a write bitline.

21. The IC device according to claim 14 , wherein one electrode of a source electrode and a drain electrode of the second transistor is directly electrically connected to a read wordline.

22. The IC device according to claim 21 , wherein another electrode of the source electrode and the drain electrode of the second transistor is directly electrically connected to a read bitline.

23. An integrated circuit (IC) device, comprising:
a first memory cell comprising a first transistor, a second transistor stacked over the first transistor, and a first capacitor connected to one of a source electrode and a drain electrode of the first transistor;
a second memory cell comprising a third transistor, a fourth transistor stacked over the third transistor, and a second capacitor connect

Assignees

• Intel Corp

Inventors

• Sharma Abhishek A
• Alzate-Vinasco Juan G
• Hamzaoglu Fatih
• Sell Bernhard
• Wang Pei-Hua
• Le Van H
• Kavalieros Jack T
• Ghani Tahir
• Arslan Umut
• Lajoie Travis W
• Ku Chieh-Jen

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title