Contact over active gate structures using directed self-assembly for advanced integrated circuit structure fabrication

Patent metadata

Field	Value
Publication number	US-12237223-B2
Application number	US-202017033483-A
Country	US
Kind code	B2
Filing date	Sep 25, 2020
Priority date	Sep 25, 2020
Publication date	Feb 25, 2025
Grant date	Feb 25, 2025

Abstract

Contact over active gate (COAG) structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A remnant of a di-block-co-polymer is over a portion of the plurality of gate structures or the plurality of conductive trench contact structures. An interlayer dielectric material is over the di-block-co-polymer, over the plurality of gate structures, and over the plurality of conductive trench contact structures. An opening in the interlayer dielectric material. A conductive structure is in the opening, the conductive structure in direct contact with a corresponding one of the trench contact structures or with a corresponding one of the gate contact structures.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon;
a plurality of conductive trench contact structures alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon;
a remnant of a di-block-co-polymer over a portion of the plurality of gate structures;
an interlayer dielectric material over the di-block-co-polymer, over the plurality of gate structures, and over the plurality of conductive trench contact structures;
an opening in the interlayer dielectric material; and
a conductive structure in the opening, the conductive structure in direct contact with a corresponding one of the trench contact structures.

2. The integrated circuit structure of claim 1 , wherein the remnant of a di-block-co-polymer comprises polystyrene (PS).

3. The integrated circuit structure of claim 1 , wherein the remnant of a di-block-co-polymer comprises poly (methyl methacrylate) (PMMA).

4. The integrated circuit structure of claim 1 , further comprising:
a plurality of dielectric spacers alternating with the plurality of gate structures and the plurality of conductive trench contact structures.

5. The integrated circuit structure of claim 1 , wherein the plurality of conductive trench contact structures and the plurality of gate structures are on a semiconductor fin.

6. An integrated circuit structure, comprising:
a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon;
a plurality of conductive trench contact structures alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon;
a remnant of a di-block-co-polymer over a portion of the plurality of gate structures;
an interlayer dielectric material over the di-block-co-polymer, over the plurality of gate structures, and over the plurality of conductive trench contact structures;
an opening in the interlayer dielectric material; and
a conductive structure in the opening, the conductive structure in direct contact with a corresponding one of the gate structures.

7. The integrated circuit structure of claim 6 , wherein the remnant of a di-block-co-polymer comprises polystyrene (PS).

8. The integrated circuit structure of claim 6 , wherein the remnant of a di-block-co-polymer comprises poly (methyl methacrylate) (PMMA).

9. The integrated circuit structure of claim 6 , further comprising:
a plurality of dielectric spacers alternating with the plurality of gate structures and the plurality of conductive trench contact structures.

10. The integrated circuit structure of claim 6 , wherein the plurality of conductive trench contact structures and the plurality of gate structures are on a semiconductor fin.

11. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon;
a plurality of conductive trench contact structures alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon;
a remnant of a di-block-co-polymer over a portion of the plurality of gate structures;
an interlayer dielectric material over the di-block-co-polymer, over the plurality of gate structures, and over the plurality of conductive trench contact structures;
an opening in the interlayer dielectric material; and
a conductive structure in the opening, the conductive structure in direct contact with a corresponding one of the trench contact structures.

12. The computing device of claim 11 , further comprising:
a memory coupled to the board.

13. The computing device of claim 11 , further comprising:
a communication chip coupled to the board.

14. The computing device of claim 11 , further comprising:
a camera coupled to the board.

15. The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

16. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon;
a plurality of conductive trench contact structures alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon;
a remnant of a di-block-co-polymer over a portion of the plurality of gate structures;
an interlayer dielectric material over the di-block-co-polymer, over the plurality of gate structures, and over the plurality of conductive trench contact structures;
an opening in the interlayer dielectric material; and
a conductive structure in the opening, the conductive structure in direct contact with a corresponding one of the gate structures.

17. The computing device of claim 16 , further comprising:
a memory coupled to the board.

18. The computing device of claim 16 , further comprising:
a communication chip coupled to the board.

19. The computing device of claim 16 , further comprising:
a camera coupled to the board.

20. The computing device of claim 16 , wherein the component is a packaged integrated circuit die.

Assignees

• Intel Corp

Inventors

• Nyhus Paul A
• Wallace Charles H
• Chandhok Manish
• Haran Mohit K
• Singh Gurpreet
• Han Eungnak
• Gstrein Florian
• Schenker Richard E
• Shykind David
• Aloysius Jinnie
• Pursel Sean

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title