Solid state high power battery disrupter

Patent metadata

Field	Value
Publication number	US-12237124-B2
Application number	US-202318374429-A
Country	US
Kind code	B2
Filing date	Sep 28, 2023
Priority date	Dec 31, 2020
Publication date	Feb 25, 2025
Grant date	Feb 25, 2025

Abstract

A power circuit breaker has a housing defining a first passage and a cross passage through the housing. A bus bar extends through the cross passage and is configured to transmit electric power and/or break transmission of the electric power through the housing. The bus bar includes at least an input section, a coin or center section, and an output section that are separable from each other. The housing aligns a solenoid piston within the first passage of the housing. The solenoid has a piston with two opposite ends, and one of the ends operates as a plunger to separate the sections of the bus bar when the solenoid is actuated. The plunger moves the coin or center section of the bus bar out of contact with the input section and the output section of the bus bar to break electrical transmission across the bus bar.

First claim

The invention claimed is:

1. A circuit breaker system, comprising:
a field effect transistor comprising a source terminal, a gate terminal, and a drain terminal attached to a substrate body to control electrical conduction there through;
a bus bar for electrical power transmission, comprising an input section connected to the source terminal and an output section connected to the drain terminal of the field effect transistor;
a separate control voltage connected to the substrate at the gate terminal, wherein a positive voltage bias on the gate terminal provides a path for the electrical power transmission through the substrate, and a negative voltage bias on the gate terminal breaks electrical power through the substrate;
wherein the substrate is doped to establish a p-n junction sufficient to withstand the electric power transmission and break the circuit from source to drain when the gate terminal is reverse biased; and
wherein a reverse biased gate terminal comprises a gate voltage that is iteratively lowered over time;
wherein the time over which the gate voltage is lowered corresponds to a response time of the substrate in establishing the p-n junction that discontinues electric power transmission from the source to the drain.

2. The circuit breaker system of claim 1 , wherein at least one of a size of the substrate, a shape of the field effect transistor, a doping profile of the substrate, and a silicon mass of the substrate corresponds to a thermal conductivity response of the substrate during electric power transmission.

3. The circuit breaker system of claim 1 , wherein the gate voltage is controlled by an electronic control unit comprising a processor and computerized memory storing electric power transmission software therein.

4. The circuit breaker system of claim 1 , further comprising an external packaging connected to the field effect transistor as a heat sink to dissipate thermal loading across the substrate.

Assignees

• Joyson Safety Systems Acquisition Llc

Inventors

• Konja Raad
• Lisseman Jason
• Moore Michael
• Cech Leonard

Classifications

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H01H71/2463

  with plunger type armatures · CPC title

• H02H7/18

  for batteries; for accumulators · CPC title

• H01H33/38

  using electromagnet · CPC title

• H01H33/12

  Auxiliary contacts on to which the arc is transferred from the main contacts (using arcing horns H01H33/20) · CPC title