Integrated assemblies and methods of forming integrated assemblies

Patent metadata

Field	Value
Publication number	US-12237013-B2
Application number	US-202117372891-A
Country	US
Kind code	B2
Filing date	Jul 12, 2021
Priority date	Jul 12, 2021
Publication date	Feb 25, 2025
Grant date	Feb 25, 2025

Abstract

Some embodiments include an integrated assembly having a vertical stack of alternating first and second levels. A panel extends through the stack. The first levels have proximal regions adjacent the panel, and have distal regions further from the panel than the proximal regions. The distal regions include conductive structures. The conductive structures have a first thickness. The proximal regions include insulative structures. The insulative structures have a second thickness at least about as large as the first thickness. Some embodiments include methods of forming integrated assemblies.

First claim

We claim:

1. An integrated assembly, comprising:
a stack of alternating first and second levels;
a panel extending through the stack; and
the first levels having proximal regions adjacent the panel, and having distal regions further from the panel than the proximal regions; the distal regions comprising conductive structures, with said conductive structures having a first thickness; the proximal regions comprising insulative structures, with said insulative structures having a second thickness at least about as large as the first thickness; and
wherein the second levels comprise void regions between the distal regions of the first levels.

2. The integrated assembly of claim 1 wherein the panel separates a first memory-block-region from a second memory-block-region.

3. The integrated assembly of claim 1 comprising channel-material-pillars extending through the stack.

4. The integrated assembly of claim 1 wherein the second thickness is larger than the first thickness.

5. The integrated assembly of claim 1 wherein the second thickness is at least about 10% larger than the first thickness.

6. The integrated assembly of claim 1 wherein the second thickness is at least about 20% larger than the first thickness.

7. The integrated assembly of claim 1 wherein the insulative structures are substantially rectangular-shaped along a cross-section.

8. The integrated assembly of claim 1 wherein the insulative structures comprise silicon and nitrogen.

9. The integrated assembly of claim 1 wherein the insulative structures comprise silicon nitride.

10. The integrated assembly of claim 1 wherein each of the conductive structures includes a tungsten-containing core and a metal-nitride-containing liner along an outer periphery of the tungsten-containing core.

11. The integrated assembly of claim 10 wherein the distal region of each of the first levels includes dielectric material along an outer periphery of the metal-nitride-containing liner.

12. The integrated assembly of claim 11 wherein the distal regions of the first levels have overall thicknesses which encompass the conductive structures and the dielectric material.

13. The integrated assembly of claim 12 wherein the second vertical widths of the insulative structures are at least about a large as the overall thicknesses of the distal regions.

14. The integrated assembly of claim 12 wherein the dielectric material is a high-k material.

15. The integrated assembly of claim 1 wherein an entirety of a periphery of the void regions is defined by only insulative material.

16. The integrated assembly of claim 1 wherein an entirety of a periphery of the void regions is spaced from, without contacting, conductive material.

17. The integrated assembly of claim 1 wherein an entirety of the panel comprises insulative material.

18. The integrated assembly of claim 1 wherein an entirety of the panel comprises a single homogeneous material.

19. An integrated assembly, comprising:
a vertical stack of alternating void levels and non-void levels;
channel-material-pillars extending vertically through the stack;
a panel extending vertically through the stack and separating a first memory-block-region from a second memory-block-region a portion of a periphery of the void levels defined by the panel; and
the non-void levels having proximal regions adjacent the panel, and having distal regions further from the panel than the proximal regions; the distal regions comprising conductive structures, with said conductive structures having a first vertical width; the proximal regions comprising insulative structures, with said insulative structures having a second vertical width at least about as large as the first vertical width.

20. The integrated assembly of claim 19 wherein the second vertical width is larger than the first vertical width.

21. The integrated assembly of claim 19 wherein the insulative structures comprise silicon nitride.

22. The integrated assembly of claim 19 wherein each of the conductive structures includes a tungsten-containing core and a metal-nitride-containing liner along an outer periphery of the tungsten-containing core.

23. The integrated assembly of claim 22 wherein the distal region of each of the non-void levels includes dielectric material along an outer periphery of the metal-nitride-containing liner.

24. The integrated assembly of claim 22 wherein the distal regions of the non-void levels have overall vertical widths which encompass the conductive structures and the dielectric material.

25. The integrated assembly of claim 24 wherein the second vertical widths of the insulative structures are at least about a large as the overall vertical widths of the distal regions.

26. The integrated assembly of claim 24 wherein the dielectric material is a high-k material.

27. The integrated assembly of claim 19 wherein an entirety of a periphery of the void levels is defined by only insulative material.

28. The integrated assembly of claim 19 wherein an entirety of a periphery of the void levels is spaced from, without contacting, conductive material.

29. The integrated assembly of claim 19 wherein an entirety of the panel comprises insulative material.

30. The integrated assembly of claim 19 wherein an entirety of the panel comprises a single homogeneous material.

31. An integrated assembly, comprising:
a vertical stack of alternating memory cell levels and insulative levels;
channel-material-pillars extending vertically through the stack;
a panel extending vertically through the stack; and
the insulative levels defined by voids having a portion of a periphery defined by at least the panel.

32. The integrated assembly of claim 31 wherein the periphery of the voids has a portion defined by the channel-material-pillars.

33. The integrated assembly of claim 31 wherein the periphery of the voids has a portion defined by the memory cell levels.

34. The integrated assembly of claim 31 wherein an entirety of the periphery of the voids is defined by only insulative material.

35. The integrated assembly of claim 31 wherein an entirety of a periphery of the void levels is spaced from, without contacting, conductive material.

36. The integrated assembly of claim 31 wherein an entirety of the panel comprises insulative material.

37. The integrated assembly of claim 31 wherein an entirety of the panel comprises a single homogeneous material.

Assignees

• Micron Technology Inc

Inventors

• Surthi Shyam
• Thorum Matthew

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title