Body tie optimization for stacked transistor amplifier

Patent metadata

Field	Value
Publication number	US-12231087-B2
Application number	US-202318182047-A
Country	US
Kind code	B2
Filing date	Mar 10, 2023
Priority date	Sep 16, 2016
Publication date	Feb 18, 2025
Grant date	Feb 18, 2025

Abstract

A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.

First claim

The invention claimed is:

1. A circuit, comprising:
a transistor stack configured to operate as an amplifier, the transistor stack comprising an input transistor in series connection with at least one transistor, the input transistor configured to receive an input RF signal at a gate of the input transistor;
wherein the input transistor is a body tied transistor having a body that is coupled to a potential, and
wherein the at least one transistor is a floating transistor having a body that is not coupled to a potential.

2. The circuit according to claim 1 , wherein the body of the input transistor is directly connected to a source of the input transistor.

3. The circuit according to claim 1 , wherein the body of the input transistor is coupled to a source of the input transistor through a resistor.

4. The circuit according to claim 1 , wherein the body of the input transistor is coupled to a fixed reference potential through an impedance of a corresponding body tie.

5. The circuit according to claim 1 , wherein the at least one transistor is an output transistor of the amplifier.

6. The circuit according to claim 1 , wherein the at least one transistor is a transistor different from an output transistor of the amplifier.

7. The circuit according to claim 1 , further comprising:
one or more additional transistors in series connection with the input transistor and the at least one transistor.

8. The circuit according to claim 7 , wherein the one or more additional transistors comprise at least one additional body tied transistor having a body that is coupled to a respective potential.

9. The circuit according to claim 7 , wherein each transistor of the one or more additional transistors is a body tied transistor having a respective body that is coupled to a respective potential.

10. The circuit according to claim 9 , wherein the respective body of each transistor of the one or more additional transistors is coupled to the respective potential of a respective source.

11. The circuit according to claim 7 , wherein the one or more additional transistors comprise at least one additional floating transistor having a body that is not coupled to a potential.

12. The circuit according to claim 1 , further comprising:
a gate capacitor connected between a gate of the floating transistor and a reference ground, the gate capacitor configured to allow a gate voltage of the floating transistor to vary along with an RF signal at a drain of the floating transistor.

13. The circuit according to claim 1 , wherein a drain of the floating transistor is coupled to a supply voltage that is configured to vary under control of a control signal.

14. The circuit according to claim 1 , wherein the input transistor and the at least one transistor are metal-oxide-semiconductor (MOS) field effect transistors (FETs), or complementary metal-oxide-semiconductor (CMOS) field effect transistors (FETs).

15. The circuit according to claim 14 , wherein the input transistor and the at least one transistor are fabricated using one of: a) silicon-on-insulator (SOI) technology, and b) silicon-on-sapphire technology (SOS).

16. The circuit according to claim 14 , wherein the input transistor and the at least one transistor are one of: a) N-type transistors, and b) P-type transistors.

17. An electronic module comprising the circuit of claim 1 .

18. An electronic system comprising the electronic module of claim 17 , wherein the electronic system comprises one of: a) a television, b) a cellular telephone, c) a personal computer, d) a workstation, e) a radio, f) a video player, g) an audio player, h) a vehicle, i) a medical device, and j) other electronic systems.

19. A method for manufacturing a stacked metal-oxide-semiconductor (MOS) power amplifier, the method comprising:
providing a substrate comprising one of: a) silicon-on-insulator substrate, and b) a silicon-on-sapphire substrate; and
manufacturing, on the substrate, a transistor stack configured to operate as the MOS power amplifier, the transistor stack comprising an input transistor in series connection with at least one transistor, the input transistor configured to receive an input RF signal at a gate of the input transistor,
wherein the input transistor is a body tied transistor having a body that is coupled to a potential, and
wherein the at least one transistor is a floating transistor having a body that is not coupled to a potential.

Assignees

• Psemi Corp

Inventors

• Willard Simon Edward
• Olson Chris
• Ranta Tero Tapio

Classifications

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H10D86/01

  Manufacture or treatment · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title