Electronic device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12230711-B2
Application number	US-202318487275-A
Country	US
Kind code	B2
Filing date	Oct 16, 2023
Priority date	Sep 18, 2019
Publication date	Feb 18, 2025
Grant date	Feb 18, 2025

Abstract

Provided are an electronic device and a method of manufacturing the same. The electronic device includes a ferroelectric crystallization layer between a substrate and a gate electrode and a crystallization prevention layer between the substrate and the ferroelectric crystallization layer. The ferroelectric crystallization layer is at least partially crystallized and includes a dielectric material having ferroelectricity or anti-ferroelectricity. Also, the crystallization prevention layer prevents crystallization in the ferroelectric crystallization layer from being spread toward the substrate.

First claim

What is claimed is:

1. An electronic device comprising:
a substrate;
a gate electrode on the substrate;
a ferroelectric crystallization layer between the gate electrode and the substrate, the ferroelectric crystallization layer being at least partially crystallized and including a dielectric material having ferroelectricity or anti-ferroelectricity;
a crystallization prevention layer between the ferroelectric crystallization layer and the substrate, the crystallization prevention layer including an amorphous dielectric material;
a high dielectric constant layer between the crystallization prevention layer and the substrate, the high dielectric constant layer including a different dielectric material than a material of the crystallization prevention layer; and
a high band gap layer between the high dielectric constant layer and the substrate, the high band gap layer including an amorphous dielectric material having a greater band gape than a material of the high dielectric constant layer.

2. The electronic device of claim 1 , wherein the ferroelectric crystallization layer includes a crystalline dielectric material having a dielectric constant that is greater than about 20.

3. The electronic device of claim 2 , wherein the ferroelectric crystallization layer includes an oxide that includes at least one of Si, Al, Hf, and Zr.

4. The electronic device of claim 1 , wherein the crystallization prevention layer has a dielectric constant that is greater than about 4.

5. The electronic device of claim 4 , wherein the crystallization prevention layer includes at least one of AlOx (0<x<1), LaOx (0<x<1), YOx (0<x<1), LaAlOx (0<x<1), TaOx (0<x<1), TiOx (0<x<1), SrTiOx (0<x<1), CaO, MgO, ZrSiO, and a 2D dielectric material.

6. The electronic device of claim 1 , wherein the high dielectric constant the layer has a higher dielectric constant than silicon oxide and includes a different dielectric material than a material of the crystallization prevention layer.

7. The electronic device of claim 1 , wherein
the substrate includes a channel element at a location corresponding to the gate electrode, and
the substrate includes a source and a drain at both sides of the channel element.

8. The electronic device of claim 7 , wherein
the channel element includes at least one of Si, Ge, SiGe, Groups III-V semiconductors, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional (2D) semiconductor material, quantum dots, and an organic semiconductor.

9. An electronic device comprising:
a substrate;
a channel element including an intermediate region between a first side and a second side;
a gate electrode on the intermediate region of the channel element;
a ferroelectric crystallization layer between the gate electrode and the channel element, the ferroelectric crystallization layer being at least partially crystallized and including a dielectric material having ferroelectricity or anti-ferroelectricity; and
a crystallization prevention layer between the ferroelectric crystallization layer and the channel element, the crystallization prevention layer including an amorphous dielectric material;
a high dielectric constant layer between the crystallization prevention layer and the substrate, the high dielectric constant layer including a different dielectric material than a material of the crystallization prevention layer; and
a high band gap layer between the high dielectric constant layer and the substrate, the high band gap layer including an amorphous dielectric material having a greater band gape than a material of the high dielectric constant layer, wherein
the channel element is a portion of the substrate or the channel element is a channel layer on the substrate.

10. The electronic device of claim 9 , wherein the ferroelectric crystallization layer includes a crystalline dielectric material having a dielectric constant that is greater than about 20.

11. The electronic device of claim 10 , wherein the ferroelectric crystallization layer includes an oxide that includes at least one of Si, Al, Hf, and Zr.

12. The electronic device of claim 9 , wherein the crystallization prevention layer has a dielectric constant that is greater than about 4.

13. The electronic device of claim 9 , wherein the high dielectric constant layer has a higher dielectric constant than silicon oxide and includes a different dielectric material than a material of the crystallization prevention layer.

14. The electronic device of claim 9 , wherein
the channel element is the portion of the substrate, and
the substrate is a semiconductor substrate.

15. The electronic device of claim 9 , wherein
the channel element is the channel layer on the substrate, and
the channel layer includes at least one of an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, quantum dots, and an organic semiconductor.

16. The electronic device of claim 9 , further comprising:
a source connected to the first side of the channel element; and
a drain connected to the second side of the channel element.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Heo Jinseong
• Kim Sangwook
• Lee Yunseong
• Jo Sanghyun
• Lee Hyangsook

Classifications

• H10D64/01338

  with a treatment, e.g. annealing, after the formation of the conductor · CPC title

• H10D64/689 Primary

  having ferroelectric layers · CPC title

• H10D64/01

  Manufacture or treatment · CPC title

• H10D30/0415

  of FETs having ferroelectric gate insulators · CPC title

• H10D64/033

  comprising ferroelectric layers · CPC title