Read collision avoidance in sequential mixed workloads

Patent metadata

Field	Value
Publication number	US-12229423-B2
Application number	US-202318348314-A
Country	US
Kind code	B2
Filing date	Jul 6, 2023
Priority date	Oct 4, 2022
Publication date	Feb 18, 2025
Grant date	Feb 18, 2025

Abstract

A data storage device processes a mixed workload including a plurality of superblocks to be written to and read from a plurality of memory dies, where each of the plurality of superblocks to be apportioned among the plurality of memory dies. The data storage device writes a first data stripe associated with a first superblock to the plurality of memory dies according to a sequential write pattern, and reads the first data stripe associated with the first superblock from the plurality of memory dies according to a sequential read pattern. The sequential write pattern causes the controller to write to the plurality of memory dies in a first order of memory dies. The sequential read pattern causes the controller to read from the plurality of memory dies in a second order of memory dies different from the first order of memory dies, thereby reducing read collisions.

First claim

What is claimed is:

1. A data storage device, comprising:
a non-volatile memory comprising a plurality of memory dies; and
a controller configured to control the non-volatile memory and communicate with a host, wherein the controller is configured to:
receive a mixed workload including a plurality of superblocks to be written to and read from the plurality of memory dies, each of the plurality of superblocks to be apportioned among the plurality of memory dies;
write a first data stripe associated with a first superblock of the plurality of superblocks to the plurality of memory dies according to a sequential write pattern; and
read the first data stripe associated with the first superblock from the plurality of memory dies according to a sequential read pattern, wherein:
the sequential write pattern causes the controller to write to the plurality of memory dies in a first order of memory dies; and
the sequential read pattern causes the controller to read from the plurality of memory dies in a second order of memory dies different from the first order of memory dies, and wherein:
the first order associated with the sequential write pattern is a random order, and the second order associated with the sequential read pattern is a sequential order; or
the controller is configured to, based on one or more future read operations, reorder the first order associated with the sequential write pattern to avoid writing to any memory dies of the plurality of memory dies while they are being read.

2. The data storage device of claim 1 , wherein the controller is further configured to, while writing the first data stripe associated with the first superblock to the plurality of memory dies, read a previously written data stripe associated with a previously written superblock of the plurality of superblocks from the plurality of memory dies.

3. The data storage device of claim 2 , wherein the controller is configured to read the previously written data stripe using the sequential read pattern.

4. The data storage device of claim 1 , wherein differences in the first order and the second order cause the controller to avoid simultaneously writing to and reading from a same memory die of the plurality of memory dies.

5. The data storage device of claim 1 , wherein:
the plurality of memory dies includes a total of N memory dies, N being an integer greater than or equal to 2; and
differences in the first order and the second order cause the controller to simultaneously write to and read from a same memory die of the plurality of memory dies fewer than N/2 times while a given data stripe is being written.

6. The data storage device of claim 1 , wherein:
the mixed workload is characterized by 50% write commands and 50% read commands; and
each write command included in the mixed workload corresponds to a respective read command included in the mixed workload.

7. The data storage device of claim 1 , wherein the controller is configured to:
detect the one or more future read operations using a sequential read ahead algorithm.

8. The data storage device of claim 7 , wherein the controller is configured to reorder the first order based on a degree of freedom associated with the first order for a given data stripe.

9. A method of operating a data storage device, the method comprising:
at a data storage device including a non-volatile memory comprising a plurality of memory dies, and a controller configured to control the non-volatile memory and communicate with a host:
receiving a mixed workload including a plurality of superblocks to be written to and read from the plurality of memory dies, each of the plurality of superblocks to be apportioned among the plurality of memory dies;
writing a first data stripe associated with a first superblock of the plurality of superblocks to the plurality of memory dies according to a sequential write pattern; and
reading the first data stripe associated with the first superblock from the plurality of memory dies according to a sequential read pattern,

wherein:
the sequential write pattern causes the controller to write to the plurality of memory dies in a first order of memory dies; and
the sequential read pattern causes the controller to read from the plurality of memory dies in a second order of memory dies different from the first order of memory dies, and

wherein:
the first order associated with the sequential write pattern alternates between:
a first sequential order having a first sequence of memory dies; and
a second sequential order having a second sequence of memory dies opposite the first sequence of memory dies; and

the second order associated with the sequential read pattern is a sequential order having the first sequence of memory dies.

10. The method of claim 9 , wherein:
the mixed workload is characterized by 50% write commands and 50% read commands; and
each write command included in the mixed workload corresponds to a respective read command included in the mixed workload.

11. A data storage device, comprising:
a non-volatile memory comprising a plurality of memory dies; and
a controller configured to control the non-volatile memory and communicate with a host, wherein the controller includes:
means for receiving a mixed workload including a plurality of superblocks to be written to and read from the plurality of memory dies, each of the plurality of superblocks to be apportioned among the plurality of memory dies;
means for writing a first data stripe associated with a first superblock of the plurality of superblocks to the plurality of memory dies according to a sequential write pattern; and
means for reading the first data stripe associated with the first superblock from the plurality of memory dies according to a sequential read pattern, and

wherein:
the sequential write pattern causes the means for writing to write to the plurality of memory dies in a first order of memory dies; and
the sequential read pattern causes the means for reading to read from the plurality of memory dies in a second order of memory dies different from the first order of memory dies, and

wherein:
the first order associated with the sequential write pattern is a sequential order that begins with a random memory die of the plurality of memory dies for each successive data stripe being written, or that begins with a memory die being identified as a last memory die used to read prior to writing a given data stripe; and
the second order associated with the sequential read pattern is a sequential order that begins with a same memory die of the plurality of memory dies for each successive data stripe being read.

Assignees

• Western Digital Tech Inc
• Sandisk Technologies Inc

Inventors

• Hutchison Neil
• Liu Haining
• Lo Jerry
• Gorobets Sergey Anatolievich

Classifications

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0635 Primary

  by changing the path, e.g. traffic rerouting, path reconfiguration · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title