Contention reduction scheduler for nand flash array with raid

Patent metadata

Field	Value
Publication number	US-2018173460-A1
Application number	US-201615380430-A
Country	US
Kind code	A1
Filing date	Dec 15, 2016
Priority date	Dec 15, 2016
Publication date	Jun 21, 2018
Grant date	—

Abstract

The present disclosure generally relates to a flash storage system, and more particularly to a scheduler in the flash storage system. The flash storage system includes a device queue, a scheduler coupled to the device queue, and a plurality of dies. In one embodiment, the scheduler pushes commands from the device queue into one or more dies of the plurality of dies for processing in read command phase and write command phase. By separately pushing read commands and write commands into dies for processing, latency is decreased and TOPS is increased.

First claim

What is claimed is:

1 . A method, comprising:
receiving a plurality of read commands and a plurality of write commands by a device queue; pushing one or more read commands of the plurality of read commands into one or more targeted dies of a plurality of dies by a scheduler; stopping pushing read commands of the plurality of read commands into the plurality of dies when a predetermined number of write commands of the plurality of write commands in the device queue have been accumulated; processing the one or more read commands in the one or more targeted dies so the plurality of dies are available for processing; and pushing the predetermined number of write commands of the plurality of write commands in the device queue into the plurality of dies for processing by the scheduler.

2 . The method of claim 1 , wherein the device queue has a queue depth of 64, 256, or 1024.

3 . The method of claim 1 , further comprising scanning the device queue by the scheduler prior to pushing one or more read commands of the plurality of read commands into one or more targeted dies.

4 . The method of claim 3 , wherein the scheduler prioritizes the plurality of read commands and the plurality of write commands as the scheduler scans the device queue.

5 . An electronic device, comprising:
a processor; a memory device, comprising:
a device queue;
a plurality of dies; and
a scheduler coupled to the device queue and the plurality of dies; and
a memory system storing instructions that, when executed by the processor, cause the electronic device to:
receive a plurality of read commands and a plurality of write commands by the device queue;
push one or more read commands of the plurality of read commands into one or more targeted dies of the plurality of dies by the scheduler;
stop pushing read commands of the plurality of read commands into the plurality of dies when a predetermined number of write commands of the plurality of write commands in the device queue have been accumulated;
process the one or more read commands in the one or more targeted dies so the plurality of dies are available for processing; and
push the predetermined number of write commands of the plurality of write commands in the device queue into the plurality of dies for processing by the scheduler.

6 . The electronic device of claim 5 , wherein the device queue has a queue depth of 64, 256, or 1024.

7 . The electronic device of claim 5 , further comprising scanning the device queue by the scheduler prior to pushing one or more read commands of the plurality of read commands into one or more targeted dies.

8 . The electronic device of claim 7 , wherein the scheduler prioritizes the plurality of read commands and the plurality of write commands as the scheduler scans the device queue.

9 . A non-transitory computer readable storage medium, containing instructions that, when executed by a processor, cause a memory device to perform read and write processes, by performing the steps of:
receiving a plurality of read commands and a plurality of write commands by a device queue; pushing one or more read commands of the plurality of read commands into one or more targeted dies of a plurality of dies by a scheduler; stopping pushing read commands of the plurality of read commands into the plurality of dies when a predetermined number of write commands of the plurality of write commands in the device queue have been accumulated; processing the one or more read commands in the one or more targeted dies so the plurality of dies are available for processing; and pushing the predetermined number of write commands of the plurality of write commands in the device queue into the plurality of dies for processing by the scheduler.

10 . The storage medium of claim 9 , wherein the device queue has a queue depth of 64, 256, or 1024.

11 . The storage medium of claim 9 , further comprising scanning the device queue by the scheduler prior to pushing one or more read commands of the plurality of read commands into one or more targeted dies.

12 . The storage medium of claim 11 , wherein the scheduler prioritizes the plurality of read commands and the plurality of write commands as the scheduler scans the device queue.

13 . A method, comprising:
receiving a plurality of read commands and a plurality of write commands by a device queue; receiving availability information of a plurality of dies by a scheduler; and pushing commands of the plurality of read commands and the plurality of write commands into dies of the plurality of dies based on a priority of the commands, if the dies are available.

14 . The method of claim 13 , wherein the device queue has a queue depth of 64, 256, or 1024.

15 . The method of claim 13 , further comprising scanning the device queue and prioritizing the plurality of read commands and the plurality of write commands the by the scheduler.

16 . The method of claim 13 , wherein the priority of the commands are based on how long the commands are in the device queue.

17 . An electronic device, comprising:
a processor; a memory device, comprising:
a device queue;
a plurality of dies; and
a scheduler coupled to the device queue and the plurality of dies; and
a memory system storing instructions that, when executed by the processor, cause the electronic device to:
receive a plurality of read commands and a plurality of write commands by the device queue;
receive availability information of the plurality of dies by the scheduler; and
push commands of the plurality of read commands and the plurality of write commands into dies of the plurality of dies based on a priority of the commands, if the dies are available.

18 . The electronic device of claim 17 , wherein the device queue has a queue depth of 64, 256, or 1024.

19 . The electronic device of claim 17 , further comprising scanning the device queue and prioritizing the plurality of read commands and the plurality of write commands the by the scheduler.

20 . The electronic device of claim 17 , wherein the priority of the commands are based on how long the commands are in the device queue.

21 . A non-transitory computer readable storage medium, containing instructions that, when executed by a processor, cause a memory device to perform read and write processes, by performing the steps of:
receiving a plurality of read commands and a plurality of write commands by a device queue; receiving availability information of a plurality of dies by a scheduler; and pushing commands of the plurality of read commands and the plurality of write commands into dies of the plurality of dies based on a priority of the commands, if the dies are available.

22 . The electronic device of claim 21 , wherein the device queue has a queue depth of 64, 256, or 1024.

23 . The electronic device of claim 21 , further comprising scanning the device queue and prioritizing the plurality of read commands and the plurality of write commands the by the scheduler.

24 . The electronic device of claim 21 , wherein the priority of the commands are based on how long the commands are in the device queue.

25 . An electronic device, comprising:
a processor; and a memory device, comprising:
means for receiving a plurality of read commands and a plurality of write commands;
means for pushing one or more read commands of the plurality of read commands into one or more

Assignees

• Western Digital Tech Inc

Inventors

• Bandic Zvonimir Z
• Qin Minghai
• Sun Chao
• Vucinic Dejan

Classifications

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title