Method and circuit for performing error detection on a clock gated register signal

Patent metadata

Field	Value
Publication number	US-12229002-B2
Application number	US-202318193446-A
Country	US
Kind code	B2
Filing date	Mar 30, 2023
Priority date	Mar 31, 2022
Publication date	Feb 18, 2025
Grant date	Feb 18, 2025

Abstract

An error detection circuit and a method for performing a cyclic redundancy check on a clock gated register signal are disclosed. The error detection circuit comprising a first register, a check bit processing logic and an error detection module. The first register is a clock gated register configured to be updated with a data signal (x) in response to a clock enabling signal. The check bit processing logic configured to, in response to a control signal, update a second register with a check bit, wherein the control signal (b) is the same as the clock enabling signal. The error detection module configured for calculating an indication bit based on at least the output of the first register and the output of the second register.

First claim

What is claimed is:

1. An error detection circuit for performing a cyclic redundancy check on a clock gated register signal, the error detection circuit comprising:
a first register, wherein the first register is a clock gated register configured to be updated with a data signal (x) in response to a clock enabling signal;
check bit processing logic configured to, in response to a control signal (b), update a second register with a check bit irrespective of whether the control signal (b) is a high value or a low value, wherein the control signal (b) is the same as the clock enabling signal; and
an error detection module configured for calculating an indication bit based on at least the output of the first register and the output of the second register.

2. The error detection circuit according to claim 1 , wherein the check bit processing logic comprises:
a controlling unit configured to select a data signal from one of the data signal (x) and a previously stored data signal (x r ) in response to the control signal; and
a check bit calculation unit configured to calculate the check bit based on the selected data signal.

3. The error detection circuit according to claim 2 , wherein the controlling unit is configured to:
receive the data signal (x) as a first input;
receive a previously stored data signal (x r ), as a second input from the first register; and
provide one of the first input or a second input to the check bit calculation unit based on a third input, wherein the third input is the control signal.

4. The error detection circuit according to claim 1 , wherein the check bit processing logic comprises:
a check bit calculation unit configured to calculate a check bit based on the data signal (x); and
a controlling unit configured to, in response to the control signal, update the second register with one of the calculated check bit (c) and a previous stored check bit (c r ).

5. The error detection circuit according to claim 4 , wherein the controlling unit is configured to:
receive the check bit (c) as a first input from the second check bit calculation unit;
receive the previously stored check bit (c r ) as a second input from the second register; and
update the second register with one of the first input or a second input based on a third input, wherein the third input is the control signal.

6. The error detection circuit according to claim 4 , wherein the controlling unit is configured to update the second register with a previously stored check bit, stored in the second register, when the control signal is low.

7. The error detection circuit according to claim 1 , wherein the first register is configured to be updated with the data signal (x) when the first register is enabled.

8. The error detection circuit according to claim 1 , wherein the check bit is an even parity bit or an odd parity bit.

9. The error detection circuit according to claim 1 , wherein the check bit processing logic updates the second register with the calculated updated check bit when the control signal is high.

10. The error detection circuit according to claim 1 , wherein the error detection module is configured to detect an error in updating the first register based on the calculated the indication bit.

11. A method of manufacturing, using an integrated circuit manufacturing system, an error detection circuit as set forth in claim 1 , the method comprising:
processing, using a layout processing system, a computer readable dataset description of the error detection circuit so as to generate a circuit layout description of an integrated circuit embodying the error detection circuit; and
manufacturing, using an integrated circuit generation system, the error detection circuit according to the circuit layout description.

12. A non-transitory computer readable storage medium having stored thereon an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture an error detection circuit as set forth in claim 1 .

13. A non-transitory computer readable storage medium having stored thereon a computer readable description of an error detection circuit as claimed in claim 1 that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying a graphics processing system including said error detection circuit.

14. A method of performing cyclic redundancy check on a clock gated register signal, the method comprising:
updating a first register with a data signal (x) in response to a clock enabling signal, wherein the first register is a clock gated register;
updating a second register with a check bit in response to a control signal by a check bit processing logic, wherein the control signal (b) is the same as the clock enabling signal and wherein the second register is updated with the check bit irrespective of whether the control signal is a high value or a low value; and
calculating an indication bit based on at least the output of the first register and the output of the second register using an error detection module.

15. The method of claim 14 , wherein updating the second register comprises:
selecting a data signal from one of the data signal (x) and a previously stored data signal (x r ) in response to a control signal by a first controlling unit;
calculating the check bit based on the selected the data signal by a first check bit calculation unit;
updating a second register with the calculated check bit in response to a control signal.

16. The method of claim 15 , wherein the second register continues to hold a previously stored check bit, stored in the second register, when the control signal is low.

17. The method of claim 14 , wherein updating the second register comprises:
calculating a check bit based on the data signal (x) by a second check bit calculation unit; and
updating the second register with one of the calculated check bit (c) and a previously stored check bit (c r ) in response to a control signal by a second controlling unit.

18. The method of claim 17 , wherein the check bit processing logic updates the second register with a previously stored check bit, stored in the second register, when the control signal is low.

19. The method of claim 14 , wherein updating the first register comprises updating with a data signal (x) when the first register is enabled using the clock enabling signal.

20. A non-transitory computer readable storage medium having stored thereon computer readable code configured to cause the method as set forth in claim 14 to be performed when the code is run on at least one processor.

Assignees

• Imagination Tech Ltd

Inventors

• Nazar Faizan
• Rovers Kenneth

Classifications

• G01R31/31727

  Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922) · CPC title

• G06F11/1004 Primary

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title