Device and method for detecting controller signal errors in flash memory

Patent metadata

Field	Value
Publication number	US-9852811-B2
Application number	US-201514851377-A
Country	US
Kind code	B2
Filing date	Sep 11, 2015
Priority date	Nov 13, 2014
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

In accordance with the disclosure, there is provided a memory device configured to implement an error detection protocol. The memory device includes a memory array and a first input for receiving a control signal corresponding to a command cycle. The memory device also includes a second input for receiving an access control signal during a command cycle and for receiving an error detection signal during the command cycle, wherein the error detection signal includes information corresponding to the access control signal. The memory device further includes control logic configured to verify the correctness of the access control signal by a comparison with the error detection signal and perform an operation on the memory array during the command cycle when the correctness of the access control signal is verified.

First claim

What is claimed is:

1. A memory device configured to implement an error detection protocol, the memory device comprising:
a memory array;
a first input for receiving a control signal corresponding to a command cycle;
a second input for receiving an access control signal during the command cycle and for receiving an error detection signal during the command cycle, wherein the error detection signal includes information corresponding to the access control signal;
control logic configured to verify the correctness of the access control signal by a comparison with the error detection signal, and to perform an operation on the memory array during the command cycle when the correctness of the access control signal is verified;
an error code generator circuit configured to generate error detection information corresponding to read data information requested by a controller as part of a read operation, the read data information including read data from the memory array; and
an output for providing the read data information and the error detection information to the controller during the command cycle.

2. The memory device of claim 1 , wherein the second input is provided for coupling to a shared data bus between the controller and the memory device.

3. The memory device of claim 2 , wherein the second input is configured to receive a plurality of command information bits provided in the access control signal, and a plurality of command error detection bits provided in the error detection signal, and further wherein the second input is configured to receive the plurality of command information bits successively followed by the plurality of command error detection bits.

4. The memory device of claim 1 , wherein the second input is provided for coupling to an error detection bus dedicated to communicating the error detection signal between the controller and the memory device.

5. The memory device of claim 1 , wherein the output is shared with the second input.

6. The memory device of claim 1 , wherein the output is configured to output the error detection information in a time multiplexed manner with the read data information.

7. The memory device of claim 1 , further comprising a second output for providing an error status signal to the controller based on a result of the comparison performed by the control logic.

8. A memory system comprising:
a controller for controlling read and write operations on a memory array of a memory device, the controller being configured to:
provide an access control signal, to the memory device, including command information indicating an operation to be performed on the memory array, and address information indicating an address at which the operation is to be performed;
generate an error detection signal including a plurality of command error detection bits corresponding to the command information and a plurality of address error detection bits corresponding to the address information; and
provide the error detection signal to the memory device; and

the memory device comprising:
an input for receiving the access control signal and for receiving the error detection signal;
control logic configured to verify the correctness of the access control signal by a comparison with the error detection signal, and to perform an operation on the memory array when the correctness of the access control signal is verified;
an error code generator circuit configured to generate error detection information corresponding to read data information requested by a controller as part of a read operation, the read data information including read data from the memory array; and
an output for providing the read data information and the error detection information to the controller during a command cycle associated with the read operation.

9. A method for implementing an error detection protocol by a memory device, the method comprising:
receiving a chip select signal corresponding to a command cycle;
receiving an access control signal and an error detection signal during the command cycle, wherein the error detection signal includes information corresponding to the access control signal;
comparing the error detection signal with the access control signal to determine that the received access control signal is correct;
performing a read operation on a memory array during the command cycle based on the access control signal;
generating an error detection code for read data read from the memory array; and
outputting the read data and a second error detection signal during the command cycle, wherein the second error detection signal includes information corresponding to the error detection code.

10. The method of claim 9 , further comprising receiving the access control signal and the error detection signal in a time multiplexed manner.

11. A memory device, comprising:
a first input for receiving an access signal;
a second input for receiving a detection signal;
control logic configured to control the access signal when the detection signal is provided to the memory;
an error code generator circuit configured to generate error detection information corresponding to read data information requested by a controller as part of a read operation, the read data information including read data from a memory array of the memory device; and
an output for providing the read data information and the error detection information to the controller during a command cycle associated with the read operation.

Assignees

• Macronix Int Co Ltd

Inventors

• Chang Kuen Long
• Chen Ken Hui
• Lo Su Chueh
• Cheng Chia-Feng

Classifications

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F11/1004

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C29/02

  Detection or location of defective auxiliary circuits, e.g. defective refresh counters · CPC title