Array substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-12225781-B2
Application number	US-202117788605-A
Country	US
Kind code	B2
Filing date	Aug 30, 2021
Priority date	Mar 11, 2021
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

An array substrate is provided. A respective pixel driving circuit of the array substrate includes a driving transistor, a storage capacitor, and a transistor having a gate electrode connected to a respective second gate line of a plurality of second gate lines, a first electrode connected to a first capacitor electrode of the storage capacitor, and a second electrode connected to a second electrode of a first reset transistor, the transistor being configured to receive a reset signal through the first reset transistor. An active layer of the driving transistor and an active layer of the transistor are spaced apart from each other by at least an insulating layer. The active layer of the driving transistor comprises a first semiconductor material. The active layer of the transistor comprises a second semiconductor material different from the first semiconductor material.

First claim

What is claimed is:

1. An array substrate, comprising a plurality of pixel driving circuits, a plurality of light emitting elements respectively connected to the plurality of pixel driving circuits, and a first connecting pad in a first signal line layer, the first connecting pad connecting the second electrode of the transistor and the second electrode of the first reset transistor;
wherein a respective pixel driving circuit comprises a driving transistor, a storage capacitor, and a transistor having a gate electrode connected to a respective second gate line of a plurality of second gate lines, a first electrode connected to a first capacitor electrode of the storage capacitor, and a second electrode connected to a second electrode of a first reset transistor, the transistor being configured to receive a reset signal through the first reset transistor;
an active layer of the driving transistor and an active layer of the transistor are spaced apart from each other by at least an insulating layer;
the active layer of the driving transistor comprises a first semiconductor material; and
the active layer of the transistor comprises a second semiconductor material different from the first semiconductor material;
wherein the first connecting pad is connected to the second electrode of the transistor through a first via extending through at least a passivation layer, and is connected to the second electrode of the first reset transistor through a second via extending through at least the passivation layer and the insulating layer.

2. The array substrate of claim 1 , wherein gate electrodes of the transistor and the first reset transistor are connected to different control signal lines in different layers, respectively.

3. The array substrate of claim 1 , wherein the respective pixel driving circuit further comprises the first reset transistor comprising a gate electrode connected to a respective reset control signal line in a present stage of a plurality of reset control signal lines, a first electrode connected to a respective first reset signal line of a plurality of first reset signal lines, and a second electrode connected to the second electrode of the transistor.

4. The array substrate of claim 1 , further comprising a node connecting line in the first signal line layer;
wherein the node connecting line connects the first electrode of the transistor to the first capacitor electrode, which functions as a gate electrode of the driving transistor.

5. An array substrate, comprising a plurality of pixel driving circuits, a plurality of light emitting elements respectively connected to the plurality of pixel driving circuits, a node connecting line in the first signal line layer, and an auxiliary capacitor electrode;
wherein a respective pixel driving circuit comprises a driving transistor, a storage capacitor, and a transistor having a gate electrode connected to a respective second gate line of a plurality of second gate lines, a first electrode connected to a first capacitor electrode of the storage capacitor, and a second electrode connected to a second electrode of a first reset transistor, the transistor being configured to receive a reset signal through the first reset transistor;
an active layer of the driving transistor and an active layer of the transistor are spaced apart from each other by at least an insulating layer;
the active layer of the driving transistor comprises a first semiconductor material; and
the active layer of the transistor comprises a second semiconductor material different from the first semiconductor material;
wherein the node connecting line connects the first electrode of the transistor to the first capacitor electrode, which functions as a gate electrode of the driving transistor;
wherein the node connecting line is connected to the auxiliary capacitor electrode through a fifth via extending through at least a passivation layer; and
wherein the array substrate further comprises an auxiliary capacitor comprising the auxiliary capacitor electrode and a portion of a respective first gate line of a plurality of first gate lines, the respective first gate line being connected to a gate electrode of a first transistor and a gate electrode of a second transistor.

6. The array substrate of claim 4 , wherein the node connecting line crosses over the respective second gate line in a present stage.

7. An array substrate, comprising a plurality of pixel driving circuits, a plurality of light emitting elements respectively connected to the plurality of pixel driving circuits, and a node connecting line in a first signal line layer;
wherein a respective pixel driving circuit comprises a driving transistor, a storage capacitor, and a transistor having a gate electrode connected to a respective second gate line of a plurality of second gate lines, a first electrode connected to a first capacitor electrode of the storage capacitor, and a second electrode connected to a second electrode of a first reset transistor, the transistor being configured to receive a reset signal through the first reset transistor;
an active layer of the driving transistor and an active layer of the transistor are spaced apart from each other by at least an insulating layer;
the active layer of the driving transistor comprises a first semiconductor material; and
the active layer of the transistor comprises a second semiconductor material different from the first semiconductor material;
wherein the respective second gate line comprises a first branch and a second branch respectively in two different layers;
the first branch is in a same layer as a second capacitor electrode of the storage capacitor;
the second branch is in a same layer as a plurality of first reset signal lines, a respective first reset signal line of the plurality of first reset signal lines is configured to provide a reset signal to the first electrode of the transistor; and
the node connecting line crosses over the first branch and the second branch in a present stage.

8. The array substrate of claim 1 , wherein the respective pixel driving circuit further comprises a second transistor comprising a gate electrode connected to a respective first gate line of a plurality of first gate lines, a first electrode connected to the second electrode of the transistor and the second electrode of the first reset transistor, and a second electrode connected to a second electrode of a driving transistor.

9. The array substrate of claim 8 , wherein the respective first gate line is in a layer different from the respective second gate line; and
the respective first gate line is in a same layer as a plurality of reset control signal lines, a respective reset control signal line in a present stage of a plurality of reset control signal lines being connected to a gate electrode of the first reset transistor.

10. The array substrate of claim 1 , wherein the respective pixel driving circuit further comprises:
the first reset transistor comprising a gate electrode connected to a respective reset control signal line in a present stage of a plurality of reset control signal lines, a first electrode connected to a respective first reset signal line of a plurality of first reset signal lines, and a second electrode connected to the second electrode of the transistor; and
a second reset transistor comprising a gate electrode connected to a respective reset control signal line in a next stage of a plurality of reset control signal lines, a first electrode connected to a respective second reset signal line of a plurality of second reset signal lines, and a second electrode connected to an anode of a respective light emitting element of the plurality of light emitting eleme

Assignees

• Boe Technology Group Co Ltd

Inventors

• Feng Yu
• Liu Libin
• Lu Jiangnan

Classifications

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6745

  Polycrystalline or microcrystalline silicon · CPC title

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• G09G3/32

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title