Thin film transistor and fabricating method thereof, array substrate and display device

Patent metadata

Field	Value
Publication number	US-2020161402-A1
Application number	US-201916619446-A
Country	US
Kind code	A1
Filing date	May 21, 2019
Priority date	May 21, 2018
Publication date	May 21, 2020
Grant date	—

Abstract

A thin film transistor includes: a substrate base; a first gate electrode at a side of the substrate base; an active layer at a side of the first gate electrode away from the substrate base; a second gate electrode at a side of the active layer away from the substrate base; and a source/drain electrode at a side of the second gate electrode away from the substrate base. An orthographic projection of the source/drain electrode on the substrate base is at least partially overlapped with an orthographic projection of the second gate electrode on the substrate base.

First claim

1 . A thin film transistor comprising:
a substrate base; a first gate electrode at a side of the substrate base; an active layer at a side of the first gate electrode away from the substrate base; a second gate electrode at a side of the active layer away from the substrate base; and a source/drain electrode at a side of the second gate electrode away from the substrate base, wherein an orthographic projection of the source/drain electrode on the substrate base is at least partially overlapped with an orthographic projection of the second gate electrode on the substrate base.

2 . The thin film transistor according to claim 1 , further comprising:
a buffer layer at a side of the first gate electrode away from the substrate base; a gate insulating layer at a side of the active layer away from the substrate base; and an interlayer dielectric layer at a side of the second gate electrode away from the substrate base.

3 . The thin film transistor according to claim 2 , further comprising a connection electrode at a side of the interlayer dielectric layer away from the substrate base,
wherein the buffer layer comprises a first via hole penetrating through the buffer layer, and an orthographic projection of the first via hole on the substrate base is at least partially overlapped with an orthographic projection of the first gate electrode on the substrate base, wherein the interlayer dielectric layer comprises a second via hole and a third via hole penetrating through the interlayer dielectric layer, an orthographic projection of the second via hole on the substrate base is at least partially overlapped with the orthographic projection of the active layer on the substrate base, and an orthographic projection of the third via hole on the substrate base covers the orthographic projection of the first via hole on the substrate base, the orthographic projection of the third via hole is at least partially overlapped with the orthographic projection of the second gate electrode, wherein the connection electrode is electrically connected to the first gate electrode through the first via hole and the third via hole, and is electrically connected to the second gate electrode through the third via.

4 . The thin film transistor according to claim 1 , wherein an orthographic projection of the first gate electrode on the substrate covers an orthographic projection of the active layer on the substrate base.

5 . The thin film transistor according to claim 1 , wherein the active layer comprises a metal oxide semiconductor material.

6 . The thin film transistor according to claim 3 , wherein the connection electrode comprises a transparent conductive material.

7 . The thin film transistor according to claim 3 , further comprising:
a passivation layer at a side of the source/drain electrode away from the substrate base; and a light shielding layer at a side of the passivation layer away from the substrate base, the light shielding layer being configured to absorb and/or reflect ambient light.

8 . An array substrate comprising:
a thin film transistor according to claim 1 ; and a photosensitive element at a side of the source/drain electrode of the thin film transistor away from the substrate base, wherein a first electrode of the photosensitive element is connected with one of the source/drain electrode of the thin film transistor.

9 . The array substrate according to claim 8 , further comprising a leading-out layer at a side of the photosensitive element away from the substrate base,
wherein a second electrode of the photosensitive element is connected to the leading-out layer.

10 . The array substrate according to claim 9 , further comprising a conductive layer in the same layer as the second gate electrode in the thin film transistor,
wherein the conductive layer is connected to the leading-out layer, and an orthographic projection of the conductive layer on the substrate base is at least partially overlapped with an orthographic projection of the source/drain electrode of the thin film transistor on the substrate base.

11 . The array substrate according to claim 10 , further comprising a connection layer in the same layer as the source/drain electrode of the thin film transistor,
wherein the conductive layer is connected to the leading-out layer through the connection layer.

12 . A display device comprising an array substrate according to claim 8 .

13 . A fabricating method of a thin film transistor comprising:
providing a substrate base; forming a first gate electrode at a side of the substrate base; forming an active layer at a side of the first gate electrode away from the substrate base; forming a second gate electrode at a side of the active layer away from the substrate base; and forming a source/drain electrode at a side of the second gate electrode away from the substrate base, wherein an orthographic projection of the source/drain electrode on the substrate base is at least partially overlapped with an orthographic projection of the second gate electrode on the substrate base.

14 . The method according to claim 13 , wherein forming an active layer at a side of the first gate electrode away from the substrate base comprises:
forming a buffer layer at a side of the first gate electrode away from the substrate base, in which the buffer layer comprises a first via hole penetrating through the buffer layer, and an orthographic projection of the first via hole on the substrate base is at least partially overlapped with the orthographic projection of the first gate electrode on the substrate base; and forming the active layer at a side of the buffer layer away from the substrate base.

15 . The method according to claim 14 , further comprising:
forming a passivation layer at a side of the source/drain electrode away from the substrate base; and forming a light shielding layer at a side of the passivation layer away from the substrate base, the light shielding layer being configured to absorb and/or reflect ambient light.

16 . The method according to claim 13 , wherein forming a source/drain electrode at a side of the second gate electrode away from the substrate base comprises:
forming an interlayer dielectric layer at a side of the second gate electrode away from the substrate base, in which the interlayer dielectric layer comprises a second via hole and a third via hole which penetrate through the interlayer dielectric layer, an orthographic projection of the second via hole on the substrate base is at least partially overlapped with an orthographic projection of the active layer on the substrate base, and an orthographic projection of the third via hole on the substrate base covers the orthographic projection of the first via hole on the substrate base; and forming the source/drain electrode and a connection electrode at a side of the interlayer dielectric layer away from the substrate base, in which the connection electrode is electrically connected to the first gate electrode through the first via hole and the third via hole and is electrically connected to the second gate electrode through the third via hole.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Ling
• Lin Yicheng
• Gai Cuili
• Xu Pan

Classifications

• H01L29/66969

  Electricity · mapped topic

• H01L23/5226

  Electricity · mapped topic

• H01L29/78648

  Electricity · mapped topic

• H01L27/1225

  Electricity · mapped topic

• H01L29/41733

  Electricity · mapped topic