Methods and apparatus to perform a pseudo-S3 protocol to update firmware and/or activate new firmware with a warm reset

Patent metadata

Field	Value
Publication number	US-12223308-B2
Application number	US-202018040147-A
Country	US
Kind code	B2
Filing date	Aug 25, 2020
Priority date	Aug 25, 2020
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

Methods, apparatus, systems, and articles of manufacture to perform a pseudo-S3 protocol to update firmware and/or activate new firmware with a warm reset are disclosed. An example apparatus includes an advanced configuration and power interface (ACPI) to: initiate a pseudo-sleep event in response to identifying a firmware update; and assert a power button event, the power button event to cause an operating system (OS) to prepare to enter into a sleep state; a basic input/output system (BIOS) to: initiate a warm reset in response to the OS preparing to enter the sleep state, the warm reset to update firmware according to the firmware update; and transmit a wake vector to the OS to continue operation.

First claim

What is claimed is:

1. An apparatus comprising:
an advanced configuration and power interface (ACPI) to:
initiate a pseudo-sleep event in response to identifying a firmware update; and
assert a power button event, the power button event to cause an operating system (OS) to prepare to enter into a sleep state; and

a basic input/output system (BIOS) to:
initiate a warm reset in response to the OS preparing to enter the sleep state, the warm reset to update firmware according to the firmware update without entering the sleep state or performing a full reboot; and
transmit a wake vector to the OS to continue operation.

2. The apparatus of claim 1 , further including a baseboard management controller (BMC) to set a general purpose input/output (GPIO) as active when the firmware update is obtained, the ACPI to identify the firmware update based on a status of the GPIO.

3. The apparatus of claim 1 , wherein the OS triggers an interrupt when preparing to enter into the sleep state, further including an interrupt handler to:
in response to the interrupt, determine that the pseudo-sleep event was initiated; and
trigger the BIOS to initiate the warm reset in response to the determination.

4. The apparatus of claim 1 , wherein the wake vector causes the OS to return to operation.

5. The apparatus of claim 1 , further including memory, the memory including a first section dedicated to the BIOS and a second section dedicated to the OS.

6. The apparatus of claim 5 , wherein the BIOS is to update the firmware using the first section of the memory and keeping the second section of the memory intact.

7. The apparatus of claim 1 , wherein the BIOS is to reset a second sleep state flag when at least one of (a) a pseudo-sleep flag is not set or (b) a memory topology has changed, the pseudo-sleep flag identifying that the pseudo-sleep event was initiated.

8. The apparatus of claim 1 , wherein the firmware is implemented by at least one of BMC, the ACPI, the BIOS, a processor, a manageability engine, a solid state device, or a network-on-chip.

9. A non-transitory computer readable storage medium comprising instructions which, when executed, cause a basic input/output system (BIOS) to at least:
in response to (a) a pseudo-sleep event being initiated and (b) an operating system preparing for a sleep state, initiate a warm reset to update firmware according to a firmware update without entering the sleep state or performing a full reboot; and
transmit a wake vector to the operating system after the firmware is updated.

10. The non-transitory computer readable storage medium of claim 9 , wherein the instructions are to cause the BIOS to update the firmware using a first section of memory dedicated to the BIOS and keeping a second section of the memory intact, the second section of memory dedicated to the operating system.

11. The non-transitory computer readable storage medium of claim 9 , wherein the instructions are to cause the BIOS to reset a second sleep state flag when at least one of (a) a pseudo-sleep flag is not set or (b) a memory topology has changed, the pseudo-sleep flag identifying that the pseudo-sleep event was initiated.

12. The non-transitory computer readable storage medium of claim 9 , wherein the firmware is implemented by at least one of a baseboard management controller (BMC), an advanced configuration and power interface (ACPI), the BIOS, a processor, a manageability engine, a solid state device, or a network-on-chip.

13. The non-transitory computer readable storage medium of claim 9 , wherein the instructions are to cause the BIOS to:
determine that the pseudo-sleep event is initiated based on a flag; and
determine that the operating system is preparing to enter the sleep state based on the operating system triggering an interrupt.

14. An apparatus comprising:
means for, in response to (a) a pseudo-sleep event being initiated and (b) an operating system preparing to enter a sleep state, initiating a warm reset to update firmware according to a firmware update without entering the sleep state or performing a full reboot; and
means for waking up the operating system with a wake vector after the firmware is updated.

15. The apparatus of claim 14 , further including means for storing data, the storing means including a first section dedicated to a basic input/output system (BIOS) and a second section dedicated to the operating system.

16. The apparatus of claim 15 , wherein the waking means is to update the firmware using the first section of the storing means and keeping the second section of the storing means intact.

17. The apparatus of claim 14 , wherein the waking means is to reset a second sleep state flag when at least one of (a) a pseudo-sleep flag is not set or (b) a memory topology has changed, the pseudo-sleep flag identifying that the pseudo-sleep event was initiated.

18. The apparatus of claim 15 , wherein the firmware is implemented by at least one of a baseboard management controller (BMC), an advanced configuration and power interface (ACPI), a BIOS, a processor, a manageability engine, a solid state device, or a network-on-chip.

19. The apparatus of claim 14 , wherein the initiating means is to:
determine that the pseudo-sleep event is initiated based on a flag; and
determine that the operating system is preparing to enter the sleep state based on the operating system triggering an interrupt.

20. The apparatus of claim 14 , wherein the sleep state is an S3 sleep state.

Assignees

• Intel Corp

Inventors

• Kumar Mohan
• Jayakumar Sarathy
• Wang Brett Peng
• Raj Ashok
• Nachimuthu Murugasamy

Classifications

• G06F9/4406

  Loading of operating system · CPC title

• G06F9/4403

  Processor initialisation · CPC title

• G06F9/4401

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title

• G06F9/4418

  Suspend and resume; Hibernate and awake · CPC title

• G06F8/65 Primary

  Updates (security arrangements therefor G06F21/57) · CPC title