Systems and methods for mapping hardware FIFO to processor address space

Patent metadata

Field	Value
Publication number	US-12222884-B2
Application number	US-202217813123-A
Country	US
Kind code	B2
Filing date	Jul 18, 2022
Priority date	Nov 17, 2016
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

An apparatus for a microprocessor computer system and method for configuring the same where said microprocessor computer system comprises a processor core and at least one hardware buffer FIFO with memory-mapped head and tail that handles data movement among the processor cores, networks, raw data input and outputs, and memory. The method for configuring said microprocessor computer system comprises utilizing a FIFO auxiliary processor to process said data traversing said hardware FIFO; utilizing said hardware FIFOs to efficiently pipe data through functional blocks; and utilizing a FIFO controller to perform DMA operations that include non-unit-stride access patterns and transfers among processor cores, networks, raw data input and outputs, memory, and other memory-mapped hardware FIFOs.

First claim

What is claimed is:

1. A method of configuring a microprocessor computer system, wherein said microprocessor computer system comprises:
a plurality of external data streams, each associated with a distinct memory-mapped FIFO; and
a processor core that processes multiple sequential iterations of a vector operation, each iteration requiring the processing of a datum from each of the data streams before proceeding to the next iteration;
said method comprising, for each iteration of the vector operation, configuring said vector operation to access each memory-mapped FIFO in turn and to stall if any such access is invalid.

2. The method of claim 1 , wherein the plurality of external data streams is a plurality of external input data streams;
wherein each of said input data streams in enqueued in a distinct memory-mapped FIFO and said processor core must dequeue and process one datum from each memory-mapped FIFO for each iteration;
wherein an invalid access of a memory-mapped FIFO comprises executing a read operation against an empty FIFO; and
wherein iterating said vector operation results in processing the external input data streams.

3. The method of claim 1 , wherein the plurality of external data streams is a plurality of external output data streams;
wherein each of said output data streams is dequeued from a distinct memory-mapped FIFO and said processor core must enqueue one datum to each memory-mapped FIFO for each iteration;
wherein an invalid access of a memory-mapped FIFO comprises executing a write operation against an full FIFO; and
wherein iterating said vector operation results in generating the external output data streams.

4. The method of claim 1 , wherein said external data streams are synchronously sampled data from a multiplicity of analog-to-digital converters.

5. The method of claim 1 , wherein each said memory-mapped FIFO is accessed by said processor core as an address.

6. The method of claim 5 , wherein the said processor core reads said memory-mapped FIFO by reading said address.

7. The method of claim 6 , wherein said step of reading said address dequeues a value at the head of a queue.

8. The method of claim 5 , wherein said processor core writes to said memory-mapped FIFO by writing said address.

9. The method of claim 8 , wherein said step of writing said address enqueues a value at the head of a queue.

10. The method of claim 9 , wherein said processor core will stall when writing to a full memory-mapped FIFO.

11. The method of claim 1 , wherein when said plurality of external data streams are stored sequentially in said memory-mapped FIFO, said memory-mapped FIFO is addressed by specifying a vector stride of zero.

12. The method of claim 11 , wherein said step of specifying a vector stride of zero reads a same address repeatedly to access all data in said memory-mapped FIFO.

13. The method of claim 1 , wherein when said plurality of external data streams are to be stored sequentially in said memory-mapped FIFO, a write to said memory-mapped FIFO will fill said memory-mapped FIFO when a vector stride of zero is specified.

14. The method of claim 1 , wherein said processor core will read and dequeue data at the head of a non-empty said memory-mapped FIFO and will block said read operation when said memory-mapped FIFO is empty.

15. The method of claim 1 , wherein said processor core will read data at the head of a non-empty said memory-mapped FIFO and will block said read operation when said memory-mapped FIFO is empty.

16. The method of claim 1 , wherein said processor core will read data at the head of a non-empty said memory-mapped FIFO and return an invalid value when said memory-mapped FIFO is empty.

17. The method of claim 1 , wherein said processor core will read and dequeue data at the head of a non-empty said memory-mapped FIFO and will return an invalid value when said memory-mapped FIFO is empty.

18. The method of claim 17 , wherein said processor core remains un-stalled when said invalid value is returned.

19. The method of claim 16 , wherein said processor core remains un-stalled when said invalid value is returned.

Assignees

• Us Gov Air Force
• Us Air Force

Inventors

• Linderman Mark H
• Wu Qing
• Fitzgerald Dennis

Classifications

• F16J15/32

  with elastic sealings, e.g. O-rings · CPC title

• F16C33/741

  by means of a fluid · CPC title

• G06F13/4031

  with arbitration · CPC title

• G06F13/4081

  Live connection to bus, e.g. hot-plugging (current or voltage limitation during live insertion H02H9/004) · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title