Systems and method for mapping FIFOs to processor address space

Patent metadata

Field	Value
Publication number	US-10521390-B2
Application number	US-201715804525-A
Country	US
Kind code	B2
Filing date	Nov 6, 2017
Priority date	Nov 17, 2016
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

An apparatus for a microprocessor computer system and method for configuring the same where said microprocessor computer system comprises a processor core and at least one hardware buffer FIFO with memory-mapped head and tail that handles data movement among the processor cores, networks, raw data input and outputs, and memory. The method for configuring said microprocessor computer system comprises utilizing a FIFO auxiliary processor to process said data traversing said hardware FIFO; utilizing said hardware FIFOs to efficiently pipe data through functional blocks; and utilizing a FIFO controller to perform DMA operations that include non-unit-stride access patterns and transfers among processor cores, networks, raw data input and outputs, memory, and other memory-mapped hardware FIFOs.

First claim

That which is claimed is:

1. A microprocessor computer system comprising:
a processor core capable of at least one of
reading data from a separate storage means by presenting an address and retrieving data; and
writing data to a separate storage means by presenting an address and data to be stored by said storage means;

a storage means comprising at least one bank of at least one hardware first in first out (FIFO), said hardware FIFO further comprising a head, a tail, and a buffer comprising any number of additional buffer locations to hold data enqueued in the FIFO:
wherein at least one of said FIFO head and FIFO tail is addressable by said processor core and mapped to at least one fixed memory address; and
busses and control signals to operably couple said processor core and said hardware FIFO, wherein said busses transfer addresses and data between said processor core and said hardware FIFO, and said control signals indicate failed attempts to write to said hardware FIFO when it is full and failed attempts to read from said hardware FIFO when it is empty;

a microprocessor computer system further comprising a controllable FIFO,
wherein said controllable FIFO further comprises a FIFO controller, and
wherein said FIFO controller further comprises at least one of a state machine and a programmable microcontroller that is configured to control operations on said hardware FIFO;
wherein said microprocessor computer system further comprising a FIFO bank;

a memory hierarchy comprising at least one cache memory and at least one higher-level memory within a memory hierarchy above said cache memory wherein
said cache memory operably couples said processor core to said higher-level memory;
wherein said control signals further indicate to said processor core that said processor core's requested read operation has resulted in a cache miss such that the requested data is not immediately available; and
wherein said control signals further indicate to said processor core that said processor core's requested write operation cannot immediately be executed.

2. The microprocessor computer system according to claim 1 further comprising at least one arbiter that mediates contention for bus and signal resources shared by at least two of said processor core, said hardware FIFO, said cache memory, and said higher-level memory.

3. The microprocessor computer system according to claim 2 wherein said processor core includes caches through which said processor core accesses said at least one of said hardware FIFO.

4. The microprocessor computer system according to claim 3 wherein said read operation on said FIFO head comprises at least one of a blocking dequeueing read, a blocking non-dequeuing read, a non-blocking dequeueing read, and a non-blocking non-dequeuing read.

5. The microprocessor computer system according to claim 4 wherein said processor core indicates the type of said read operation to be performed by mapping a different address to said FIFO head for each type of said read operation.

6. The microprocessor computer system according to claim 5 wherein said write operation on said FIFO tail comprises at least one of a blocking enqueueing write, a non-blocking enqueueing write, and a non-blocking non-enqueueing write.

7. The microprocessor computer system according to claim 6 wherein said processor core indicates the type of said write operation to be performed by mapping a different address to said FIFO tail for each type of said write operation.

8. The microprocessor computer system according to claim 7 , wherein attempts by said processor core to perform an enqueuing write on a full FIFO are treated like a cache miss that stalls an invoking processor core thread until capacity is available; and
attempts by said processor core to perform a dequeuing read on an empty FIFO are treated like a cache miss that stalls an invoking processor core thread until data is available.

9. The microprocessor computer system according to claim 8 wherein a write operation to said buffer comprises a block-oriented data transfer.

10. The microprocessor computer system according to claim 9 wherein a read operation from said buffer comprises a block-oriented data retrieval operation.

11. The microprocessor computer system according to claim 10 wherein said FIFO controller further comprises an auxiliary processor configured by said processor core to control at least one of:
manipulation of data enqueued in said hardware FIFO;
transfers of data into said hardware FIFO from at least one of cache memory, other memory, external networks, raw data inputs, and other hardware FIFOs; and
transfers of data from said hardware FIFO to at least one of cache memory, other memory, external networks, raw data inputs, and other hardware FIFOs.

12. The microprocessor computer system according to claim 11 wherein said auxiliary processor is of a processor type selected from the group consisting of a field-programmable gate array (FPGA), a microprocessor, and a microcontroller.

13. The microprocessor computer system according to claim 12 wherein addresses for at least one of transfers to cache, memory and other FIFOS, and transfers from cache, memory, and other FIFOs use addresses computed by said FIFO controller.

14. The microprocessor computer system according to claim 13 further comprising at least one other hardware FIFOs
wherein said FIFO controller of said controllable FIFO is further configured to at least one of:
write data from said controllable FIFO's head to at least one of said other FIFO's tail, and
read data from at least one of said other FIFO's head to said controllable FIFO's tail.

15. The microprocessor system according to claim 14 wherein at least one of said memory-mapped FIFO head and tail is pinned at a logical buffer address managed by the cache memory.

16. The microprocessor computer system according to claim 15 further comprising:
at least one additional buffer that is located apart from said hardware FIFO and that uses an alternate memory to expand the capacity of said hardware FIFO, and
busses and signals to transfer data between said hardware FIFO and said additional buffer.

17. The microprocessor computer system according to claim 16 wherein said FIFO controller adjusts the size of said additional buffer.

18. The microprocessor computer system according to claim 17 further comprising:
at least one additional processor core; and
a data communications network;
wherein said at least one additional processor core exchanges data over said data communications network with said processor core by means of said hardware FIFOs.

19. The microprocessor computer system according to claim 18 wherein said at least one additional processor core comprises a fixed functionality computational block.

20. The microprocessor computer system according to claim 19 , wherein said fixed functionality computational block consumes data from at least one memory-mapped hardware FIFO and produces data that is enqueued on at least one memory-mapped hardware FIFO.

21. The microprocessor computer system according to claim 20 wherein said FIFO buffer further comprises a functional block that processes data as it moves from said FIFO tail towards said FIFO head.

22. A method of configuring a microprocessor computer system, wherein said microprocessor computer system comprises a processor core capable of at least one of reading data from a storage means by presenting a memory address and r

Assignees

• Goverment Of The United States As Represented By Secretary Of The Air Force
• Us Air Force

Inventors

• Linderman Mark H
• Wu Qing
• Fitzgerald Dennis

Classifications

• G06F13/4031

  with arbitration · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/4081

  Live connection to bus, e.g. hot-plugging (current or voltage limitation during live insertion H02H9/004) · CPC title

• G06F13/404 Primary

  with address mapping · CPC title

• F16J15/32

  with elastic sealings, e.g. O-rings · CPC title