Memory module with data buffering

Patent metadata

Field	Value
Publication number	US-12222878-B2
Application number	US-202117403832-A
Country	US
Kind code	B2
Filing date	Aug 16, 2021
Priority date	Mar 5, 2004
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

A memory module operable to communicate data with a memory controller via a memory bus. The memory module comprises memory devices and logic configurable to receive and register a set of input address and control signals associated with a read or write memory command and to output data transfer control signals. The memory module further comprises circuitry coupled between the memory bus and the memory devices. The circuitry is configurable to be in any of a plurality of states including a first state and a second state, and to transition from the first state to the second state in response to the data transfer control signals. The circuitry in the first state is configured to disable signal communication through the circuitry. The circuitry in the second state is configured to transfer the data signals associated with the read or write command in accordance with a transfer time budget of the memory module.

First claim

We claim:

1. A memory module operable in a computer system, the computer system including a memory controller coupled to a memory bus, the memory bus including address and control signal lines and data signal lines, the memory module comprising:
a printed circuit board having a plurality of edge connections configured to be electrically coupled to a corresponding plurality of contacts of a module slot of the computer system to provide electrical connections between the memory bus and components of the memory module mounted on the printed circuit board;
logic coupled to the printed circuit board and configurable to receive input address and control signals associated with a read or write memory command via the address and control signal lines and to output registered address and control signals corresponding to the input address and control signals, the input address and control signals including a plurality of input chip select signals and other input address and control signals, the plurality of input chip select signals at least including a first input chip select signal and a second input chip select signal, the first input chip select signal having an active value and the second input chip select signal having an inactive value, the registered address and control signals including a plurality of registered chip select signals and other registered address and control signals, the plurality of registered chip select signals at least including a first registered chip select signal corresponding to the first input chip select signal and a second registered chip select signal corresponding to the second input chip select signal, the first registered chip select signal having an active value and the second registered chip select signal having an inactive value, wherein the logic is further configurable to output data transfer control signals associated with the read or write memory command;
memory devices mounted on the printed circuit board, the memory devices at least including first memory devices and second memory devices, wherein the first memory devices are configured to receive the first registered chip select signal and the other registered address and control signals, and to receive or output data signals associated with the read or write command via memory device data signal lines on the printed circuit board, the memory device data signal lines corresponding, respectively, to the data signal lines in the memory bus, and wherein the second memory devices are configured to receive the second registered chip select signal and the other registered address and control signals; and
circuitry coupled between the memory devices and the data signal lines in the memory bus, and configurable to be in any of a plurality of states including a first state and a second state, wherein:
the circuitry is configurable to transition from the first state to the second state in response to the data transfer control signals;
the circuitry in the first state is configured to disable signal communication through the circuitry;
the circuitry in the second state is configured to transfer the data signals associated with the read or write command between the memory device data signal lines and the data signal lines in the memory bus via registered data transfers in accordance with a transfer time budget of the memory module, the data signals including respective sets of consecutively transmitted data bits corresponding to respective data signal lines in the memory bus, each respective set of consecutively transmitted data bits being successively transferred through the circuitry between a respective data signal line in the memory bus and a corresponding one of the memory device data signal lines;
the transfer time budget of the memory module includes a predetermined amount of time delay associated with the registered data transfers through the circuitry; and
an overall CAS latency of the memory module is greater than an actual operational CAS latency of each of the memory devices by at least the predetermined amount of time delay.

2. The memory module of claim 1 , wherein each of the memory devices has a corresponding load, and the circuitry is configured to isolate the loads of the memory devices from the memory bus.

3. The memory module of claim 1 , wherein each of the memory devices is a double data rate synchronous dynamic random access memory (SDRAM) device that is 4-bits or 8-bits wide, and wherein the first memory devices form a first rank and the second memory devices form a second rank, each of the first rank and the second rank being 32-bits, 64-bits or 72-bits wide.

4. The memory module of claim 1 , wherein each of the memory devices is 4-bits wide, and wherein the memory devices are configured in 8-bit-wide pairs.

5. The memory module of claim 1 , wherein the registered data transfers are between the memory devices and the memory bus through the circuitry.

6. The memory module of claim 1 , wherein the respective set of consecutively transmitted data bits are successively transferred between the circuitry and the respective data signal line in the memory bus at a specific data rate, and successively transferred between the circuitry and the corresponding memory device data signal line on the module board at the specific data rate.

7. The memory module of claim 1 , further comprising a phase locked loop clock driver configured to output a clock signal in response to one or more signals received from the memory controller, wherein the predetermined amount of time delay is at least one clock cycle time delay.

8. The memory module of claim 7 , wherein the memory devices are dynamic random access memory devices configured to operate synchronously with the clock signal, and wherein each memory device in the first memory devices is configured to receive or output a respective set of data strobes and to receive or output data bits on both edges of each of the respective set of data strobes.

9. The memory module of claim 1 , wherein the circuitry includes data paths that are disabled when the circuitry is in the first state and enabled when the circuitry is in the second state.

10. The memory module of claim 9 , wherein the data paths are disabled when no data signals associated with any memory command are being transferred through the circuitry.

11. The memory module of claim 9 , wherein the memory module has a specified data rate, and wherein the data signals are transferred through the data paths at the specified data rate.

12. The memory module of claim 1 , wherein the circuitry in response to the data transfer control signals is configured to transition from the first state to the second state before transferring the data signals associated with the read or write command and to transition from the second state to the first state after transferring the data signals associated with the read or write command through the circuitry.

13. A memory module operable in a computer system, the computer system including a memory controller, at least one module slot, and a memory bus between the memory controller and the at least one module slot, the memory bus including address and control signal lines, data signal lines and data strobe signal lines, the memory module comprising:
a printed circuit board having a plurality of edge connections configured to be electrically coupled to a corresponding plurality of contacts of a module slot of the computer system to provide electrical connections between the memory bus and components of the memory module mounted on the printed circuit board;
memory devices mounted on the printed circuit board, the memory devices including at least first memory d

Assignees

• Netlist Inc

Inventors

• Solomon Jefferey C
• Bhakta Jayesh R

Classifications

• G11C15/00

  Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores · CPC title

• G11C7/1072

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/4243

  with synchronous protocol · CPC title

• G06F12/00

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title