Array substrate, fabricating method therefor and display panel

Patent metadata

Field	Value
Publication number	US-12219851-B2
Application number	US-202318321657-A
Country	US
Kind code	B2
Filing date	May 22, 2023
Priority date	Mar 18, 2020
Publication date	Feb 4, 2025
Grant date	Feb 4, 2025

Abstract

The present disclosure provides an array substrate including a driving circuit board, and a first electrode layer, an insulating layer, and an anode structure sequentially stacked thereon. The anode structure includes a reflective layer, an intermediate dielectric layer, and a transparent conductive layer sequentially provided in a direction away from the driving circuit board. The array substrate has first, second, and third pixel regions. The anode structure includes first, second, and third anode structures. The first electrode layer includes first, second and third sub-portions. The first, second and third anode structures are coupled with the first, second and third sub-portions through first, second and third via holes in the insulating layer, respectively. A surface of the insulating layer in contact with the first, second and third anode structures is flush; and a thickness of the intermediate dielectric layer in the second, first and third anode structures increases sequentially.

First claim

What is claimed is:

1. An array substrate, comprising a driving circuit board, and a first electrode layer, an insulating layer, and an anode structure sequentially stacked on the driving circuit board; the anode structure comprising a reflective layer, an intermediate dielectric layer, and a transparent conductive layer sequentially provided in a direction away from the driving circuit board, wherein
the array substrate has a first pixel region, a second pixel region, and a third pixel region;
the anode structure comprises a first anode structure in the first pixel region, a second anode structure in the second pixel region, and a third anode structure in the third pixel region;
the first electrode layer comprises a first sub-portion in the first pixel region, a second sub-portion in the second pixel region, and a third sub-portion in the third pixel region; the first anode structure is coupled with the first sub-portion through a first via hole provided in the insulating layer, the second anode structure is coupled with the second sub-portion through a second via hole provided in the insulating layer, and the third anode structure is coupled with the third sub-portion through a third via hole provided in the insulating layer;
an orthographic projection of the first via hole on the driving circuit board is located outside an orthographic projection of the intermediate dielectric layer on the driving circuit board, and an uppermost end of the first via hole is in contact with a lowermost surface of the transparent conductive layer in the first anode structure;
an orthographic projection of the second via hole on the driving circuit board is located outside the orthographic projection of the intermediate dielectric layer on the driving circuit board, and an uppermost end of the second via hole is in contact with a lowermost surface of the transparent conductive layer in the second anode structure; and
an orthographic projection of the third via hole on the driving circuit board is located outside the orthographic projection of the intermediate dielectric layer on the driving circuit board, and an uppermost end of the third via hole is in contact with a lowermost surface of the transparent conductive layer in third anode structure.

2. The array substrate of claim 1 , wherein in each of the first anode structure, the second anode structure and the third anode structure, a first side surface of the reflective layer is in contact with and attached to the insulating layer,
the intermediate dielectric layer covers all outer side surfaces of the reflective layer except the first side surface, and a peripheral edge region of the intermediate dielectric layer is in contact with and attached to the insulating layer.

3. The array substrate of claim 1 , wherein the transparent conductive layer covers a whole outer side of the intermediate dielectric layer away from the reflective layer, and a peripheral edge region of the transparent conductive layer is in contact with and attached to the insulating layer.

4. The array substrate of claim 1 , wherein the reflective layer comprises a first metal layer and a first protective layer on a side of the first metal layer away from the transparent conductive layer,
a thickness of the first metal layer is larger than a thickness of the first protective layer.

5. The array substrate of claim 4 , wherein the first electrode layer comprises a second metal layer.

6. The array substrate of claim 5 , wherein the first electrode layer further comprises a second protective layer on a side of the second metal layer away from the anode structure.

7. The array substrate of claim 6 , wherein the first electrode layer further comprises a third protective layer on a side of the second metal layer close to the anode structure.

8. The array substrate of claim 7 , wherein the second protective layer comprises a first sub-protective layer and a second sub-protective layer; the third protective layer comprises a first sub-protective layer and a second sub-protective layer; the first sub-protective layer and the second sub-protective layer of each of the second protective layer and the third protective layer are sequentially stacked in a direction away from the second metal layer; and
a material of the first sub-protective layer of each of the second protective layer and the third protective layer comprises titanium, and a material of the second sub-protective layer of each of the second protective layer and the third protective layer comprises titanium nitride.

9. The array substrate of claim 4 , wherein the first protective layer comprises a first sub-protective layer and a second sub-protective layer, and the first sub-protective layer and the second sub-protective layer are sequentially stacked in a direction away from the first metal layer; and
a material of the first sub-protective layer comprises titanium, and a material of the second sub-protective layer comprises titanium nitride.

10. The array substrate of claim 1 , wherein the first sub-portion, the second sub-portion, and the third sub-portion are coupled with pixel circuits in the driving circuit board through via holes, respectively;
a surface of the insulating layer that is in contact with the first anode structure, the second anode structure, and the third anode structure is flush; and a thickness of the intermediate dielectric layer in the second anode structure, a thickness of the intermediate dielectric layer in the first anode structure, and a thickness of the intermediate dielectric layer in the third anode structure increases in sequence.

11. The array substrate of claim 1 , wherein surfaces of the first sub-portion, the second sub-portion and the third sub-portion away from the driving circuit board are flush;
the first via hole in the insulating layer has one end coupled to a portion, which is in contact with the insulating layer, of the transparent conductive layer in the first anode structure, and another end coupled to the surface of the first sub-portion away from the driving circuit board;
the second via hole in the insulating layer has one end coupled to a portion, which is in contact with the insulating layer, of the transparent conductive layer in the second anode structure, and another end coupled to the surface of the second sub-portion away from the driving circuit board; and
the third via hole in the insulating layer has one end coupled to a portion, which is in contact with the insulating layer, of the transparent conductive layer in the third anode structure, and another end coupled to the surface of the third sub-portion away from the driving circuit board.

12. The array substrate of claim 1 , wherein in each of the first anode structure, the second anode structure, and the third anode structure, an orthogonal projection of the reflective layer on the driving circuit board is within an orthogonal projection of the transparent conductive layer on the driving circuit board.

13. The array substrate of claim 1 , wherein the first via hole, the second via hole, and the third via hole are filled with tungsten.

14. A display panel, comprising the array substrate according to claim 1 , and further comprising a light-emitting functional layer, a cathode layer, and an encapsulation layer sequentially provided on the array substrate; wherein
the light-emitting functional layer comprises a red light-emitting functional layer, a green light-emitting functional layer, and a blue light-emitting functional layer, which are provided in the first pixel region, the second pixel region and the third pixel region of the array substrate, respectively; and

Assignees

• Boe Technology Group Co Ltd

Inventors

• Liu Li
• Lu Pengcheng
• Shi Rongrong
• Tian Yuanlan
• Wei Junbo
• Zhang Dacheng

Classifications

• H10K59/878

  comprising reflective means · CPC title

• H10K59/876

  comprising a resonant cavity structure, e.g. Bragg reflector pair · CPC title

• H10K59/80518

  Reflective anodes, e.g. ITO combined with thick metallic layers · CPC title

• H10K59/353 Primary

  characterised by the geometrical arrangement of the RGB subpixels · CPC title

• H10K59/123 Primary

  Connection of the pixel electrodes to the thin film transistors [TFT] · CPC title