Manufacturing method of semiconductor structure and semiconductor structure

Patent metadata

Field	Value
Publication number	US-12218220-B2
Application number	US-202217661359-A
Country	US
Kind code	B2
Filing date	Apr 29, 2022
Priority date	Jan 17, 2022
Publication date	Feb 4, 2025
Grant date	Feb 4, 2025

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: depositing a thin-film stacked structure on a substrate; forming a first hole in the thin-film stacked structure; growing an epitaxial silicon pillar in the first hole; etching the thin-film stacked structure and the epitaxial silicon pillar along a first direction to form a first trench, the first trench passing through a center of the epitaxial silicon pillar and dividing the epitaxial silicon pillar into a first half pillar and a second half pillar; forming a first isolation layer; forming a first channel region of a first doping type, and forming a second channel region of a second doping type; and forming a gate dielectric layer and a gate conductive layer on a surface of each of the first channel region and the second channel region.

First claim

The invention claimed is:

1. A manufacturing method of a semiconductor structure, comprising:
providing a substrate, and depositing a thin-film stacked structure on the substrate;
forming a first hole in the thin-film stacked structure, the first hole extending through the thin-film stacked structure along a stacking direction of the thin-film stacked structure, and a bottom of the first hole exposing the substrate;
growing an epitaxial silicon pillar in the first hole;
etching the thin-film stacked structure and the epitaxial silicon pillar along a first direction to form a first trench, the first trench passing through a center of the epitaxial silicon pillar and dividing the epitaxial silicon pillar into a first half pillar and a second half pillar;
forming a first isolation layer, the first isolation layer filling the first trench;
forming a first channel region of a first doping type in a sidewall of the first half pillar away from the first trench, and forming a second channel region of a second doping type in a sidewall of the second half pillar away from the first trench, one of the first doping type and the second doping type being an N type, and the other one being a P type; and
forming a gate dielectric layer and a gate conductive layer on a surface of each of the first channel region and the second channel region.

2. The manufacturing method of a semiconductor structure according to claim 1 , wherein the forming a first hole in the thin-film stacked structure comprises:
forming, on the thin-film stacked structure, a patterned mask layer with a hole pattern; and etching the thin-film stacked structure along the hole pattern until the substrate is exposed, thereby forming the first hole.

3. The manufacturing method of a semiconductor structure according to claim 2 , wherein the growing an epitaxial silicon pillar in the first hole comprises:
growing, in the first hole, the epitaxial silicon pillar with a selective epitaxial growth method from a surface of the substrate exposed by the first hole, until a top surface of the epitaxial silicon pillar is not lower than a top surface of the patterned mask layer.

4. The manufacturing method of a semiconductor structure according to claim 1 , wherein a width of the first trench is 30-90% of a maximum width of the epitaxial silicon pillar in a second direction.

5. The manufacturing method of a semiconductor structure according to claim 1 , wherein the depositing a thin-film stacked structure on the substrate comprises:
sequentially depositing a first insulating layer, a sacrificial layer, a second insulating layer and a mask covering layer on the substrate, a thickness of the sacrificial layer being 50-90% of a thickness of the thin-film stacked structure.

6. The manufacturing method of a semiconductor structure according to claim 5 , after the forming a first isolation layer, further comprising: forming a first opening in the thin-film stacked structure at a first side of the first isolation layer, the first opening exposing at least a part of the sacrificial layer.

7. The manufacturing method of a semiconductor structure according to claim 6 , after the forming a first opening, further comprising:
removing, with wet etching along the first opening, the sacrificial layer at a side of the first isolation layer close to the first opening, to expose the sidewall of the first half pillar away from the first trench.

8. The manufacturing method of a semiconductor structure according to claim 7 , wherein the forming a first channel region of a first doping type in a sidewall of the first half pillar away from the first trench comprises:
selectively removing, after the exposing the sidewall of the first half pillar away from the first trench, a part of the first half pillar with wet etching, to form a first gap in the sidewall of the first half pillar away from the first trench; and forming the first channel region of the first doping type at the first gap with a selective epitaxial growth method and an in-situ doping method.

9. The manufacturing method of a semiconductor structure according to claim 8 , wherein the gate dielectric layer comprises a first gate dielectric layer and a second gate dielectric layer, and the forming a gate dielectric layer and a gate conductive layer on a surface of each of the first channel region and the second channel region comprises:
forming the first gate dielectric layer on a sidewall of the first channel region to cover the surface of the first channel region.

10. The manufacturing method of a semiconductor structure according to claim 9 , after the forming the first gate dielectric layer on a sidewall of the first channel region to cover the surface of the first channel region, further comprising: forming a second opening in the thin-film stacked structure at a second side of the first isolation layer, the second opening exposing at least a part of the sacrificial layer.

11. The manufacturing method of a semiconductor structure according to claim 10 , after the forming a second opening, further comprising:
removing, with wet etching along the second opening, the sacrificial layer at a side of the first isolation layer close to the second opening, to expose the sidewall of the second half pillar away from the first trench.

12. The manufacturing method of a semiconductor structure according to claim 11 , wherein the forming a second channel region of a second doping type in a sidewall of the second half pillar away from the first trench comprises:
selectively removing, after the exposing the sidewall of the second half pillar away from the first trench, a part of the second half pillar with wet etching, to form a second gap in the sidewall of the second half pillar away from the first trench; and forming the second channel region of the second doping type at the second gap with the selective epitaxial growth method and the in-situ doping method.

13. The manufacturing method of a semiconductor structure according to claim 12 , wherein the forming a gate dielectric layer and a gate conductive layer on a surface of each of the first channel region and the second channel region comprises:
forming the second gate dielectric layer on a sidewall of the second channel region to cover the surface of the second channel region.

14. The manufacturing method of a semiconductor structure according to claim 13 , wherein the forming a gate dielectric layer and a gate conductive layer on a surface of each of the first channel region and the second channel region comprises:
filling, after the forming the second gate dielectric layer on a sidewall of the second channel region to cover the surface of the second channel region, the gate conductive layer to positions where the sacrificial layer is removed, along the first opening and the second opening, wherein the gate conductive layer covers the first gate dielectric layer and the second gate dielectric layer.

15. The manufacturing method of a semiconductor structure according to claim 14 , after the forming the gate conductive layer, further comprising:
forming a second trench in a side of the first trench close to the first opening, and forming a third trench in a side of the first trench close to the second opening, the second trench and the third trench being parallel to the first trench and extending toward the first direction, and a bottom of each of the second trench and the third trench exposing the first insulating layer to separate the gate conductive layer; taking a part of the gate conductive layer close to the first channel region as a first gate electrode, and taking a part of

Assignees

• Changxin Memory Tech Inc

Inventors

• Guo Shuai
• Zuo Mingguang
• Bai Shijie

Classifications

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/0128

  Manufacturing their channels · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D62/235

  of IGFETs (IGFETs having buried channels H10D30/637) · CPC title