Apparatus, system and method to detect and improve an input clock performance of a memory device

Patent metadata

Field	Value
Publication number	US-12217787-B2
Application number	US-202117349854-A
Country	US
Kind code	B2
Filing date	Jun 16, 2021
Priority date	Jun 16, 2021
Publication date	Feb 4, 2025
Grant date	Feb 4, 2025

Abstract

A method, apparatus and system. The method includes: performing one or more training iterations to tune a target clock signal frequency to be applied at a memory device, each of the one or more training iterations including: causing a modified clock signal frequency to be applied at the memory device; and decoding a quality feedback message from the memory device including an indication of a performance of the clock signal frequency at the memory device; and in response to a determination that the performance of the clock signal frequency falls within a target performance range of the memory device and that the clock signal frequency is below the target clock signal frequency, performing a subsequent training iteration of the one or more training iterations, and otherwise causing application at the memory device, during a memory operation, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within the target performance range.

First claim

What is claims is:

1. An integrated circuit of a memory subsystem including:
an input and output (I/O) interface to connect to a memory device;
one or more processors coupled to the I/O interface and configured to:
perform one or more training iterations to tune a target clock signal frequency to be applied at the memory device, each of the one or more training iterations including:
causing a modified clock signal frequency to be applied at the memory device; and
decoding a quality feedback message from the memory device including an indication of a performance of the clock signal frequency at the memory device; and

in response to a determination that the performance of the clock signal frequency falls within a target performance range of the memory device and that the clock signal frequency is below the target clock signal frequency, perform a subsequent training iteration of the one or more training iterations, and otherwise cause application at the memory device, during a memory operation, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within the target performance range.

2. The integrated circuit of claim 1 , wherein:
the memory device is part of a memory module including a plurality of memory devices;
the one or more processors are to perform the one or more training iterations to tune the target clock signal frequency to be applied at the memory devices;
causing includes causing the modified clock signal frequency to be applied at the memory devices; and
decoding a quality feedback message from the memory device includes decoding a respective quality feedback message from respective ones of the memory devices, each quality feedback message including an indication of a performance of the clock signal frequency at respective ones of the memory devices; and
the one or more processors are further to, in response to a determination that the performance of the clock signal at said respective ones of the memory devices falls within a corresponding target performance range the respective ones of the memory devices, and that the clock signal frequency is below the target clock signal frequency, perform a subsequent training iteration of the one or more training iterations, and otherwise cause application at the memory devices, during memory operations, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within target performance ranges of the memory devices.

3. The integrated circuit of claim 2 , wherein the memory module includes a dual inline memory module (DIMM), and the memory devices include respective dynamic random access memories (DRAMs).

4. The integrated circuit of claim 3 , wherein the DIMM includes a register coupled to the DRAMs, the one or more processors to cause the modified clock signal frequency to be applied by sending a command through the register to modify clock signal frequency at the DRAMs.

5. The integrated circuit of claim 2 , wherein each of the one or more training iterations further includes modifying a termination level of at least one of the memory devices based on the clock signal frequency and prior to decoding.

6. The integrated circuit of claim 1 , wherein the one or more training iterations include a plurality of training iterations, the one or more processors to:
modify the clock signal frequency at each successive training iteration to a successively higher clock signal frequency until a determination that the performance of the clock signal does not fall within the target performance range; and
in response to the determination that the performance of the clock signal does not fall within the target performance range, cause the application at the memory device, during the memory operation, of the highest clock signal frequency corresponding to the training iteration for which performance of the clock signal was within the target performance range.

7. The integrated circuit of claim 1 , wherein the quality feedback message includes encoded data corresponding to a maximum voltage detected at the memory device based on the clock signal frequency.

8. The integrated circuit of claim 7 , wherein the encoded data consists of n-bit binary data, the one or more processors to receive the n-bit binary data through n respective data (DQ) buses connected to the I/O interface.

9. The integrated circuit of claim 7 , wherein the target performance range of the memory device corresponds to a minimum acceptable voltage level at the memory device based on the clock signal frequency.

10. The integrated circuit of claim 1 , wherein the one or more processors are to determine the target performance range from serial presence detect (SPD) data corresponding to the memory device.

11. The integrated circuit of claim 1 , wherein the one or more processors are at least one of: to determine whether the performance of the clock signal frequency falls within the target performance range of the memory device or to receive, through the I/O interface, information based on a determination as to whether the performance of the clock signal frequency falls within the target performance range of the memory device.

12. The integrated circuit of claim 1 , wherein the I/O interface and the one or more processors are part of a memory controller, the integrated circuit further including a central processing unit connected to the memory controller through the I/O interface.

13. The integrated circuit of claim 1 , wherein the one or more processors are to tune the target clock signal frequency during initialization of the memory device.

14. A method to be performed at an integrated circuit of a memory subsystem, the method including:
performing one or more training iterations to tune a target clock signal frequency to be applied at a memory device, each of the one or more training iterations including:
causing a modified clock signal frequency to be applied at the memory device; and
decoding a quality feedback message from the memory device including an indication of a performance of the clock signal frequency at the memory device; and

in response to a determination that the performance of the clock signal frequency falls within a target performance range of the memory device and that the clock signal frequency is below the target clock signal frequency, performing a subsequent training iteration of the one or more training iterations, and otherwise causing application at the memory device, during a memory operation, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within the target performance range.

15. The method of claim 14 , wherein:
the memory device is part of a memory module including a plurality of memory devices;
performing includes performing the one or more training iterations to tune the target clock signal frequency to be applied at the memory devices;
causing includes causing the modified clock signal frequency to be applied at the memory devices; and
decoding a quality feedback message from the memory device includes decoding a respective quality feedback message from respective ones of the memory devices, each quality feedback message including an indication of a performance of the clock signal frequency at respective ones of the memory devices; and
the method further includes, in response to a determination that the performance of the clock signal at said respective ones of the memory devices falls within a corresponding target performance range the respective ones of the memory dev

Assignees

• Intel Corp

Inventors

• Kumar Arvind A
• Mccall James Alexander
• Nale Bill H
• Goles John R
• Eugenio Dean-Dexter R

Classifications

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C11/4072

  Circuits for initialization, powering up or down, clearing memory or presetting · CPC title

• G11C2207/2254

  Calibration · CPC title