Machine-learning based clustering for clock tree synthesis

Patent metadata

Field	Value
Publication number	US-11645441-B1
Application number	US-202017139657-A
Country	US
Kind code	B1
Filing date	Dec 31, 2020
Priority date	Dec 31, 2020
Publication date	May 9, 2023
Grant date	May 9, 2023

Abstract

Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of clock sinks during clock tree synthesis. An integrated circuit (IC) design comprising a clock net that includes a plurality of clock sinks is accessed. An initial number of clusters to generate from the set of clock sinks is determined using a machine-learning model. A first set of clusters is generated from the set of clocks sinks and includes the initial number of clusters. A timing analysis is performed to determine whether each cluster in the first set of clusters satisfies design rule constraints. The initial number of clusters is adjusted based on the timing analysis and a clustering solution is generated based on the adjusted number of clusters.

First claim

What is claimed is:

1. A system comprising:
one or more processors of a machine; and
a computer-storage medium storing instructions, which when executed by the one or more processors, configure the machine to perform operations comprising:
accessing, from memory, an integrated circuit design comprising a clock net comprising a set of clock sinks;
determining, using a machine-learning model, an initial number of clusters to generate from the set of clock sinks such that each cluster satisfies one or more design rule constraints;
generating a first set of clusters from the set of clock sinks of the clock net, the first set of clusters comprising the initial number of clusters;
performing an initial timing analysis to evaluate the first set of clusters to determine whether each cluster in the first set of clusters satisfies the one or more design rule constraints;
adjusting the initial number of clusters based on a result of the initial timing analysis, the adjusting of the initial number of clusters comprising decrementing the initial number of clusters based on determining each cluster in the first set of clusters satisfies the one or more design rule constraints, the adjusting of the initial number of clusters resulting in an adjusted number of clusters; and
generating a clustering solution for the clock net based on the adjusted number of clusters.

2. The system of claim 1 , wherein adjusting the initial number of clusters comprises:
determining whether each cluster in the first set of clusters satisfies the one or more design rule constraints based on the initial timing analysis.

3. The system of claim 1 , wherein:
the adjusting the initial number of clusters further comprises:
generating a second set of clusters comprising a second number of clusters, the second number of clusters resulting from decrementing the initial number of clusters; and
based on determining each cluster in the second set of clusters satisfies the one or more design rule constraints, decrementing the second number of clusters.

4. The system of claim 3 , wherein the adjusting the initial number of clusters further comprises:
generating a third set of clusters comprising a third number of clusters, the third number of clusters resulting from decrementing the second number of clusters;
determining at least one cluster in the third set of clusters fails to satisfy the one or more design rule constraints based on a subsequent timing analysis; and
based on determining that at least one cluster in the third set of clusters fails to satisfy the one or more design rule constraints, selecting the second number of clusters as the adjusted number of clusters.

5. The system of claim 1 , wherein the machine-learning model is generated by using one or more machine-learning algorithms to analyze training data to find correlations among a set of identified features that affect whether clusters satisfy design rule constraints.

6. The system of claim 5 , wherein:
the training data comprises clusters of clock sinks that are labeled according to respective satisfaction of the design rule constraints; and
the set of identified features includes one or more of: driver location, driver size, input slew of driver, number of sinks, sink sizes, sink locations, bounding box area, average clock net radius, routing topology, total wirelength, and resistance and capacitance characteristics.

7. The system of claim 1 , wherein the one or more design rule constraints comprise at least one timing target.

8. The system of claim 1 , wherein the operations further comprise generating a layout instance based on the clustering solution, the layout instance defining physical layout dimensions of the integrated circuit design.

9. A method comprising:
accessing, from memory, an integrated circuit design comprising a clock net comprising a set of clock sinks;
determining, using a machine-learning model, an initial number of clusters to generate from the set of clock sinks such that each cluster satisfies one or more design rule constraints;
generating, using one or more processors of a machine, a first set of clusters by clustering the set of clock sinks of the clock net, the first set of clusters comprising the initial number of clusters;
adjusting the initial number of clusters based on whether each cluster in the first set of clusters satisfies one or more design rule constraints, the adjusting of the initial number of clusters comprising decrementing the initial number of clusters based on determining each cluster in the set of clusters satisfies the one or more design rule constraints, the adjusting of the initial number of clusters resulting in an adjusted number of clusters;
generating a clustering solution for the clock net based on the adjusted number of clusters; and
generating a layout instance based on the clustering solution, the layout instance defining physical layout dimensions of the integrated circuit design.

10. The method of claim 9 , wherein the adjusting the initial number of clusters comprises:
determining whether each cluster in the first set of clusters satisfies the one or more design rule constraints based on a timing analysis.

11. The method of claim 9 , wherein:
the adjusting the initial number of clusters further comprises:
generating a second set of clusters comprising a second number of clusters, the second number of clusters resulting from decrementing the initial number of clusters; and
based on determining each cluster in the second set of clusters satisfies the one or more design rule constraints, decrementing the second number of clusters.

12. The method of claim 11 , wherein the adjusting the initial number of clusters further comprises:
generating a third set of clusters comprising a third number of clusters, the third number of clusters resulting from decrementing the second number of clusters;
determining at least one cluster in the third set of clusters fails to satisfy the one or more design rule constraints based on a subsequent timing analysis; and
based on determining that at least one cluster in the third set of clusters fails to satisfy the one or more design rule constraints, selecting the second number of clusters as the adjusted number of clusters.

13. The method of claim 9 , further comprising generating the machine-learning model by using one or more machine-learning algorithms to analyze training data to find correlations among a set of identified features that affect whether clusters satisfy design rule constraints.

14. The method of claim 13 , wherein:
the training data comprises clusters of clock sinks that are labeled according to respective satisfaction of the design rule constraints; and
the set of identified features include one or more of: driver location, driver size, input slew of driver, number of sinks, sink sizes, sink locations, bounding box area, average clock net radius, routing topology, total wirelength, and resistance and capacitance characteristics.

15. The method of claim 9 , wherein the one or more design rule constraints comprise at least one timing target.

16. A system comprising:
one or more processors of a machine; and
a computer storage medium storing instructions, which when executed by the machine, cause the machine to perform operations comprising:
accessing, from memory, an integrated circuit design comprising a clock net comprising a set of clock sinks;
determining, using a machine-learning model, an initial number of clusters to generate from the set of clock sinks such that each cluster satisfies one or more design rule constrain

Assignees

• Cadence Design Systems Inc

Inventors

• Jiang Bentian
• Viswanathan Natarajan
• Li Zhuo
• Ding Yi-Xiao

Classifications

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/396

  Clock trees · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/27 Primary

  using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model · CPC title

• G06N20/00

  Machine learning · CPC title