Driving circuit, driving method, display device and display control method

Patent metadata

Field	Value
Publication number	US-12217705-B2
Application number	US-202218025521-A
Country	US
Kind code	B2
Filing date	Jun 24, 2022
Priority date	Jun 24, 2022
Publication date	Feb 4, 2025
Grant date	Feb 4, 2025

Abstract

A driving circuit, a driving method, a display device, and a display control method are provided. The driving circuit includes multi-stage driving units and an on/off control circuit. Each of the driving units includes an input end and a driving signal output end, and each of the driving units is configured for outputting a corresponding driving signal via the driving signal output end according to an input signal provided by the input end. The input end of a first-stage driving unit is electrically connected to a start signal end. The on/off control circuit is electrically connected to an on/off control end and input ends of the multi-stage driving units, and configured for controlling the electric connection or electric disconnection of the input ends of the multi-stage driving units under the control of an on/off control signal provided by the on/off control end.

First claim

What is claimed is:

1. A driving circuit, comprising multi-stage driving units and an on/off control circuit; wherein
each of the multi-stage driving units comprises an input end and a driving signal output end, and configured for outputting, according to an input signal provided by the input end, a corresponding driving signal via the driving signal output end;
an input end of a first-stage driving unit of the multi-stage driving units is electrically connected to a start signal end;
the on/off control circuit is electrically connected to an on/off control end and the input ends of the multi-stage driving units, and configured for controlling, under the control of an on/off control signal provided by the on/off control end, electric connection or electric disconnection of the input ends of the multi-stage driving units, to control the multi-stage driving units to output valid driving signals in a first half of a frame time, and control the multi-stage driving units to output the valid driving signals in turn in a second half of the frame time;
the driving circuit comprises N-stage driving units, the N being a positive integer greater than 1; wherein the on/off control circuit comprises N−1 on/off control transistors;
a control electrode of an n th on/off control transistor is electrically connected to the on/off control end, a first electrode of the n th on/off control transistor is electrically connected to an input end of an n th -stage driving unit, and a second electrode of the n th on/off control transistor is electrically connected to an input end of an (n+1) th stage driving unit; and
the n+1 is less than or equal to the N, and the n is a positive integer.

2. The driving circuit according to claim 1 , wherein the driving circuit further comprises a forward scan control circuit;
the forward scan control circuit is electrically connected to a forward scan control end, a driving signal output end of the n th -stage driving unit and the input end of the (n+1) th -stage driving unit, and configured for controlling, under the control of a forward scan control signal provided by the forward scan control end, electric connection between the driving signal output end of the n th -stage driving unit and the input end of the (n+1) th -stage driving unit.

3. The driving circuit according to claim 2 , wherein the forward scan control circuit comprises N−1 forward scan control transistors;
a control electrode of an n th forward scan control transistor is electrically connected to the forward scan control end, a first electrode of the n th forward scan control transistor is electrically connected to the driving signal output end of the n th -stage driving unit, and a second electrode of the n th forward scan control transistor is electrically connected to the input end of the (n+1) th -stage driving unit.

4. The driving circuit according to claim 3 , wherein the N−1 forward scan control transistors are all n-type transistors, or the N−1 forward scan control transistors are all p-type transistors.

5. The driving circuit according to claim 1 , wherein the driving circuit further comprises a reverse scan control circuit;
the reverse scan control circuit is electrically connected to a reverse scan control end, the input end of the n th -stage driving unit and a driving signal output end of the (n+1) th -stage driving unit, and configured for controlling, under the control of a reverse scan control signal provided by the reverse scan control end, electric connection between the input end of the n th -stage driving unit and the driving signal output end of the (n+1) th -stage driving unit.

6. The driving circuit according to claim 5 , wherein the reverse scan control circuit comprises N−1 reverse scan control transistors;
a control electrode of an n th reverse scan control transistor is electrically connected to the reverse scan control end, a first electrode of the n th reverse scan control transistor is electrically connected to the input end of the n th -stage driving unit, and a second electrode of the n th reverse scan control transistor is electrically connected to the driving signal output end of the (n+1) th -stage driving unit.

7. The driving circuit according to claim 6 , wherein the N−1 reverse scan control transistors are all n-type transistors, or the N−1 reverse scan control transistors are all p-type transistors.

8. The driving circuit according to claim 1 , wherein the N−1 on/off control transistors are all n-type transistors, or the N−1 on/off control transistors are all p-type transistors.

9. The driving circuit according to claim 1 , wherein each of the driving units comprises a first node control circuit, a second node control circuit, a first energy storage circuit, a second energy storage circuit, and an output circuit;
the first node control circuit is electrically connected to a first clock signal end, an input end, a first node, a second clock signal end, a second node and a first voltage end, and configured for controlling, under the control of a first clock signal provided by the first clock signal end, electric connection between the first node and the input end, and controlling, under the control of a second clock signal provided by the second clock signal end and a potential of the second node, electric connection between the first node and the first voltage end;
the second node control circuit is electrically connected to the first node, the second node, the first clock signal end and a second voltage end, and configured for controlling, under the control of a potential of the first node, electric connection between the second node and the first clock signal end, and controlling, under the control of the first clock signal, electric connection between the second node and the second voltage end;
the first energy storage circuit is electrically connected to the first node, and configured for storing electrical energy;
the second energy storage circuit is electrically connected to the second node, and configured for storing electrical energy;
the output circuit is electrically connected to the first node, the second node, the first voltage end, the second clock signal end and the driving signal output end, and configured for controlling, under the control of the potential of the first node, electric connection between the driving signal output end and the second clock signal end, and controlling, under the control of the potential of the second node, electric connection between the driving signal output end and the first voltage end.

10. The driving circuit according to claim 1 , wherein each of the driving units comprises a first node control circuit, a second node control circuit, an output control node control circuit, a first energy storage circuit, a second energy storage circuit, and an output circuit;
the first node control circuit is electrically connected to a first clock signal end, an input end, a first node, a second clock signal end, a second node and a first voltage end, and configured for controlling, under the control of a first clock signal provided by the first clock signal end, electric connection between the first node and the input end, and controlling, under the control of a second clock signal provided by the second clock signal end and a potential of the second node, electric connection between the first node and the first voltage end;
the second node control circuit is electrically connected to the first node, the second node, the first clock signal end and a second voltage end, and configured for controlling, under the control of a potential of the first node, electric connection between the second node and the first clock signal end, and controlling, under the

Assignees

• Yunnan Invensight Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Ma Yaoxi
• Fan Longfei
• Jiang Shanghong
• Lu Pengcheng
• Yang Shengji
• Chen Xiaochuan
• Li Dachao

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2300/0852

  being a dynamic memory with more than one capacitor · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title