Semiconductor device including gate contact structure formed from gate structure

Patent metadata

Field	Value
Publication number	US-12211837-B1
Application number	US-202418615573-A
Country	US
Kind code	B1
Filing date	Mar 25, 2024
Priority date	Oct 5, 2023
Publication date	Jan 28, 2025
Grant date	Jan 28, 2025

Abstract

Provided is a semiconductor device which may include: a channel structure; a gate structure on the channel structure; and a gate contact structure on the gate structure, the gate contact structure configured to receive a gate input signal, wherein the gate contact structure is a portion of the gate structure itself, and no connection surface, interface or boundary is formed between the gate contact structure and the gate structure.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a gate structure on a channel structure;
patterning the gate structure except a portion such that the portion forms a protrusion on the patterned gate structure; and
connecting the protrusion to a metal line,
wherein the protrusion is a gate contact structure configured to receive a gate input signal for the semiconductor device.

2. The method of claim 1 , wherein the patterning the gate structure comprises:
forming a hard mask pattern on a top surface of the portion of the gate structure; and
removing the gate structure from top except the portion based on the hard mask pattern.

3. The method of claim 1 , wherein the patterning the gate structure comprises partially patterning the gate structure from top except the portion by a predetermined depth from top.

4. The method of claim 1 , wherein the gate structure comprises a gate dielectric layer, a work-function metal layer, and a gate electrode, and
wherein the pattering the gate structure is performed on the gate electrode among the gate dielectric layer, the work-function metal layer, and gate electrode.

5. The method of claim 1 , wherein the gate structure comprises a gate dielectric layer, a work-function metal layer, and a gate electrode, and
wherein the gate contact structure is a portion of the gate electrode.

6. The method of claim 1 , further comprising forming a gate capping structure to surround the protrusion,
wherein the gate capping structure comprises a dielectric material.

7. The method of claim 1 , wherein the pattering the gate structure comprises:
pattering the gate structure to form an initial protrusion on the patterned gate structure;
forming a gate capping structure to surround the initial protrusion;
removing a top portion of the initial protrusion to form the protrusion based on the gate capping structure;
forming an additional gate capping structure on a top surface of the protrusion;
forming an isolation structure on the gate capping structure; and
patterning the isolation structure and the additional capping structure to expose the top surface of the protrusion.

8. The method of claim 7 , further comprising:
forming a source/drain contract structure through the isolation structure.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Myunghoon
• Lee Jaehong
• Yun Seungchan
• Seo Kang-Ill

Classifications

• H10D88/01

  Manufacture or treatment · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/0142

  the gate conductors having different shapes or dimensions · CPC title

• H10D84/83138

  the IGFETs characterised by having different shapes or dimensions of their gate conductors · CPC title

• H10D84/832

  comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels · CPC title