Tier expansion offset

Patent metadata

Field	Value
Publication number	US-12207461-B2
Application number	US-202117558001-A
Country	US
Kind code	B2
Filing date	Dec 21, 2021
Priority date	Dec 21, 2021
Publication date	Jan 21, 2025
Grant date	Jan 21, 2025

Abstract

Systems, apparatuses, and methods may provide for technology for forming a pre-offset platform on top of a substrate. A memory block is formed, where the memory block includes a staircase area and a memory array area located adjacent the staircase area. The memory array area includes a plurality of memory pillars extending into the memory block. The staircase area has a first height, the memory array area has a second height, and a tier expansion height is defined as a difference between the second height and the first height. The pre-offset platform is located between the substrate and the staircase area of the memory block. The pre-offset platform is oriented and arranged to offset the tier expansion height so that an upper surface of the staircase area and an upper surface of the memory array area are located in a same plane.

First claim

I claim:

1. A memory device comprising:
a substrate;
a memory block located on top of the substrate, the memory block comprising:
a staircase area having a first height; and
a memory array area located adjacent the staircase area, the memory array area comprising a plurality of memory pillars extending into the memory block, wherein the memory array area has a second height different than the first height, and wherein a tier expansion height is a non-zero difference between the second height and the first height; and

a pre-offset platform located between the substrate and the staircase area of the memory block, wherein a lowermost layer of the memory array area has a lowermost surface that is coplanar with a lowermost surface of the pre-offset platform, and wherein the pre-offset platform is oriented and arranged to offset the tier expansion height so that an upper surface of the staircase area and an upper surface of the memory array area are located in a same plane.

2. The memory device of claim 1 , further comprising:
a second memory block located on top of the memory block; and
a pre-offset cap located on top of a second staircase area of the second memory block, wherein the pre-offset cap is oriented and arranged to offset a second tier expansion height so that an upper surface of the pre-offset cap and an upper surface of a second memory array area of the second memory block are located in a same plane.

3. The memory device of claim 1 , wherein the tier expansion height is due to tier expansion from formation of the plurality of memory pillars in the memory array area.

4. The memory device of claim 1 , wherein the staircase area is coupled to a plurality of decks via one or more stairwells.

5. The memory device of claim 1 , wherein a plurality of memory cells are associated with each of the plurality of memory pillars.

6. The memory device of claim 1 , wherein the pre-offset platform comprises at least one of silicon nitride (nitride) and silicon dioxide (oxide).

7. A system comprising:
a memory controller; and
a multi-deck non-volatile memory structure coupled to the memory controller, the multi-deck non-volatile memory structure comprising a plurality of decks, the multi-deck non-volatile memory structure comprising:
a substrate;
a memory block located on top of the substrate, the memory block comprising:
a staircase area having a first height; and
a memory array area located adjacent the staircase area, the memory array area comprising a plurality of memory pillars extending into the memory block, wherein the memory array area has a second height different than the first height, and wherein a tier expansion height is a non-zero difference between the second height and the first height; and

a pre-offset platform located between the substrate and the staircase area of the memory block, wherein a lowermost layer of the memory array area has a lowermost surface that is coplanar with a lowermost surface of the pre-offset platform, and wherein the pre-offset platform is oriented and arranged to offset the tier expansion height so that an upper surface of the staircase area and an upper surface of the memory array area are located in a same plane.

8. The system of claim 7 , further comprising:
a second memory block located on top of the memory block; and
a pre-offset cap located on top of a second staircase area of the second memory block, wherein the pre-offset cap is oriented and arranged to offset a second tier expansion height so that an upper surface of the pre-offset cap and an upper surface of a second memory array area of the second memory block are located in a same plane.

9. The system of claim 7 , wherein the tier expansion height is due to tier expansion from formation of the plurality of memory pillars in the memory array area.

10. The system of claim 7 , wherein the staircase area is coupled to the plurality of decks via one or more stairwells.

11. The system of claim 7 , wherein a plurality of memory cells are associated with each of the plurality of memory pillars.

12. The system of claim 7 , wherein the pre-offset platform comprises at least one of silicon nitride (nitride) and silicon dioxide (oxide).

13. A method comprising:
forming a pre-offset platform on top of a substrate;
forming a memory block, the memory block comprising:
a staircase area having a first height; and
a memory array area located adjacent the staircase area, the memory array area comprising a plurality of memory pillars extending into the memory block, wherein the memory array area has a second height different than the first height, and wherein a tier expansion height is a non-zero difference between the second height and the first height; and

wherein the pre-offset platform is located between the substrate and the staircase area of the memory block, wherein a lowermost layer of the memory array area has a lowermost surface that is coplanar with a lowermost surface of the pre-offset platform, and wherein the pre-offset platform is oriented and arranged to offset the tier expansion height so that an upper surface of the staircase area and an upper surface of the memory array area are located in a same plane.

14. The method of claim 13 , wherein the forming of the pre-offset platform further comprises:
depositing a pre-offset layer on top of the substrate;
patterning the pre-offset layer;
removing a portion of the pre-offset layer, leaving the pre-offset platform; and
cleaning the pre-offset platform.

15. The method of claim 13 , further comprising:
forming a second memory block located on top of the memory block while bypassing a chemical mechanical polishing operation between the forming of the memory block and the forming of the second memory block.

16. The method of claim 13 , further comprising:
forming a second memory block located on top of the memory block; and
forming a pre-offset cap located on top of a second staircase area of the second memory block, wherein the pre-offset cap is oriented and arranged to offset a second tier expansion height so that an upper surface of the pre-offset cap and an upper surface of a second memory array area of the second memory block are located in a same plane.

17. The method of claim 16 , wherein the forming of the pre-offset cap further comprises:
depositing a pre-offset cap layer on top of the second memory block;
patterning the pre-offset cap layer;
removing a portion of the pre-offset cap layer, leaving the pre-offset cap; and
cleaning the pre-offset cap.

18. The method of claim 13 , wherein the tier expansion height is due to tier expansion from formation of the plurality of memory pillars in the memory array area.

19. The method of claim 13 , wherein the staircase area is coupled to a plurality of decks via one or more stairwells.

20. The method of claim 13 , wherein a plurality of memory cells are associated with each of the plurality of memory pillars.

Assignees

• Intel Corp

Inventors

• Cheng Li

Classifications

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• H10B41/50

  characterised by the boundary region between the core region and the peripheral circuit region · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title