Dynamic hvpe of compositionally graded buffer layers
US-2024084479-A1 · Mar 14, 2024 · US
Wafer, optical emission device, method of producing a wafer, and method of characterizing a system for producing a wafer
US12205987B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12205987-B2 |
| Application number | US-202017595738-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 28, 2020 |
| Priority date | May 31, 2019 |
| Publication date | Jan 21, 2025 |
| Grant date | Jan 21, 2025 |
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- Title
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Abstract
Official abstract text for this publication.
A wafer includes a substrate and at least one intermediate layer formed on a surface of the substrate. The at least one intermediate layer covers the surface of the substrate at least partially. An outer surface of the at least one intermediate layer is directed away from the surface of the substrate. The wafer further includes nanostructures grown on the outer surface of the at least one intermediate layer. The at least one intermediate layer is formed in such a way that positions of growth of the nanostructures are predetermined on the outer surface of the at least one intermediate layer. At least one nanostructure material of the nanostructures is assembled at the positions of growth of the nanostructures.
First claim
Opening claim text (preview).
The invention claimed is: 1. A wafer comprising: a substrate; and at least one intermediate layer formed on a surface of the substrate, wherein the at least one intermediate layer covers the surface of the substrate at least partially, and wherein an outer surface of the at least one intermediate layer is directed away from the surface of the substrate, wherein the at least one intermediate layer is formed in such a way that positions of growth of nanostructures are predetermined on the outer surface of the at least one intermediate layer, so that at least one nanostructure material of the nanostructures is assembled at the positions of growth of the nanostructures, wherein the at least one intermediate layer is formed in such a way that the outer surface has a varying roughness with a first number of areas of the outer surface having a higher roughness and a second number of areas of the outer surface having a lower roughness than the roughness of said first number of areas, wherein the difference between the surface roughnesses of the first and second number of areas is caused by different densities of steps of atomic monolayers in the respective first and second number of areas, and wherein the nanostructures are positioned at the first number of areas of the outer surface having a higher roughness and areas therebetween are free of the nanostructures. 2. The wafer according to claim 1 , wherein the at least one intermediate layer comprises a stack of at least two layers, wherein the at least two layers each have a varying layer thickness perpendicular to the surface of the substrate, and wherein a thickness of the stack perpendicular to the surface of the substrate is constant. 3. The wafer according to claim 2 , wherein the at least one intermediate layer comprises a layer with a periodically or arbitrarily varying layer thickness perpendicular to the surface of the substrate. 4. The wafer according to claim 1 , wherein the at least one intermediate layer comprises a layer with a periodically or arbitrarily varying layer thickness perpendicular to the surface of the substrate. 5. The wafer according to claim 1 , wherein the nanostructures comprise nano-islands, droplets, nano-dashes, nano-rings, nano-posts, nano-wires, nano-ribbons, nano-rods, nano-pillars, quantum dots, biological cells and/or biomolecules. 6. The wafer according to claim 1 , wherein: the wafer is included with an optical emission device, and the optical emission device is a laser, an LED, a superradiant LED, or a single photon source.
Assignees
Inventors
Classifications
Layer structure · CPC title
- H10P14/3221Primary
Arsenides · CPC title
Silicon, silicon germanium or germanium · CPC title
Arsenides · CPC title
- H10P14/2905Primary
Silicon, silicon germanium or germanium · CPC title
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Frequently asked questions
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- What does patent US12205987B2 cover?
- A wafer includes a substrate and at least one intermediate layer formed on a surface of the substrate. The at least one intermediate layer covers the surface of the substrate at least partially. An outer surface of the at least one intermediate layer is directed away from the surface of the substrate. The wafer further includes nanostructures grown on the outer surface of the at least one inter…
- Who is the assignee on this patent?
- Univ Muenchen Tech
- What technology area does this patent fall under?
- Primary CPC classification H10P14/3221. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 21 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).