High-speed data path testing techniques for non-volatile memory
US-2018350445-A1 · Dec 6, 2018 · US
US12205658B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12205658-B2 |
| Application number | US-202117509411-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 25, 2021 |
| Priority date | Oct 25, 2021 |
| Publication date | Jan 21, 2025 |
| Grant date | Jan 21, 2025 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
Memory devices, or memory systems, described herein may include a controller (e.g., SSD controller) and a NAND memory device for storing inflight data. When the power loss event occurs, a memory system maintains (i.e., not un-select) the existing memory block being programmed at the time of power loss. The existing program operation at the event of power loss can be suspended by controller. The inflight data can be re-sent by controller directly to NAND latches, when power loss event was detected. The memory system can select a next, immediate available erased page and begin one-pulse programming to store the inflight data, without ramping down the program pump and program pulse, which was in use before the power loss event. The existing programming voltage is used to store/program the inflight data via single pulse programming. When power is restored, the inflight data is moved/programmed to another block for good data reliability.
Opening claim text (preview).
What is claimed is: 1. A method for retaining inflight data during a power loss event, the method comprising: by a controller of a memory device comprising a memory block: receiving an indication of the power loss event; suspending, based on the indication, a programming operation of inflight data to a page of the memory block; providing the inflight data to a buffer; identifying an erased page address on the memory block; programming the inflight data to the erased page; and when a power restoration event occurs, relocating the inflight data. 2. The method according to claim 1 , wherein receiving the indication comprises receiving a prefix command. 3. The method according to claim 1 , wherein the erased page defines a next immediate erased page after the erased page. 4. The method according to claim 1 , wherein programming the inflight data comprises single pulse programming. 5. The method according to claim 4 , further comprising utilizing an initial programming voltage, prior to the power loss event, to perform the single pulse programming. 6. The method according to claim 4 , wherein the single pulse programming occurs without ramping down a programming pump. 7. The method according to claim 1 , wherein the relocating the inflight data comprises programming the inflight data to a subsequent block of the memory device.
Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title
Sensing or reading circuits; Data output circuits · CPC title
using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title
External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators · CPC title
Power supply circuits · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.