Clocking scheme for reduced noise in continuous-time sigma-delta adcs preliminary class

Patent metadata

Field	Value
Publication number	US-12199629-B2
Application number	US-202318107219-A
Country	US
Kind code	B2
Filing date	Feb 8, 2023
Priority date	Feb 8, 2023
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

A circuit for a feedback system incorporates a gating mechanism to reduce flicker noise (e.g., a source for bias instability within a MEMS device) at a digital output. The gating mechanism generates a gating pulse with a delay period (e.g., a common, or fixed, delay including symmetrical rising and falling edge delays) that overrides internal delays (e.g., asymmetrical rising and falling edge delays) of a phase generator to prevent propagation delay (e.g., delay affected by jitter) from reaching subsequent feedback components (e.g., a digital-to-analog converter (DAC)) and contributing to the generation of flicker noise within the system.

First claim

What is claimed is:

1. A circuit for reducing flicker noise in a sensor signal path, comprising:
a comparison block coupled to receive a first signal within the sensor signal path and to change an output state of a comparison block output signal based on whether the first signal is transitioning between a first value and a second value;
a gating pulse generator coupled to receive the comparison block output signal, wherein a gating pulse having a delay period is output from the gating pulse generator when the output state of the comparison block output signal changes; and
a gating stage, wherein a second signal is an inverted version of the first signal, wherein the gating stage receives the gating pulse, a third signal that is based on the first signal, and a fourth signal that is based on the second signal, and wherein a transition of the third signal from a third value to a fourth value and a transition of the fourth signal from a fifth value to a sixth value are delayed based on the delay period of the gating pulse.

2. The circuit of claim 1 , wherein each of the first value, the second value, the third value, the fourth value, the fifth value, and the sixth value is a binary value.

3. The circuit of claim 2 , wherein an original transition of the third signal from the third value to the fourth value is based on the transition of the first signal, wherein the original transition of the third signal is delayed based on a delay affected by jitter, and wherein an original transition of the fourth signal from the fifth value to the sixth value is based on a transition of the second signal, and wherein the original transition of the fourth signal is delayed based on a delay affected by jitter.

4. The circuit of claim 3 , wherein the delay period of the gating pulse is greater than a maximum value for the delays affected by jitter, such that the delay period overrides the original transition of the third signal and the original transition of the fourth signal.

5. The circuit of claim 4 , wherein the delay period is two times greater than the maximum value for the delays affected by jitter.

6. The circuit of claim 1 , wherein the output state of the comparison block output signal changes when the first signal transitions between the first value and the second value.

7. The circuit of claim 6 , wherein the comparison block receives a clock signal, and wherein the comparison block output signal changes back to its previous output state based on a next transition of the clock signal after the transition of the first signal between the first value and the second value.

8. The circuit of claim 7 , wherein a period of the clock signal is shorter than or equal to an expected duration of changes in value of the first signal.

9. The circuit of claim 1 , wherein the gating pulse generator comprises a logic gate and a delay element, wherein a first input to the logic gate comprises the comparison block output signal, and wherein a second input to the logic gate comprises a delayed version of the comparison block output signal via the delay element, wherein the delayed version of the comparison block output signal is delayed by the delay period.

10. The circuit of claim 9 , wherein the gating pulse is output for a duration of the delay period from when the output state of the comparison block output signal changes.

11. The circuit of claim 10 , wherein the logic gate comprises a NOR gate.

12. The circuit of claim 11 , wherein the delayed version of the comparison block output signal is inverted prior to being provided as the second input to the logic gate.

13. The circuit of claim 1 , wherein the gating stage delays each of the transitions of the third signal and the fourth signal based on the delay period.

14. The circuit of claim 13 , wherein the gating stage comprises a first logic gate that receives the third signal and the gating pulse as inputs, and a second logic gate that receives the fourth signal and the gating pulse as inputs.

15. The circuit of claim 14 , wherein each of the first logic gate and the second logic gate is a NOR gate.

16. The circuit of claim 1 , further comprising a phase generator, wherein the first and the second signals are inputs to the phase generator, and wherein the third and the fourth signals are outputs from the phase generator.

17. The circuit of claim 16 , wherein a delay affected by jitter is based on a misalignment of transition times between the third signal and the fourth signal within the phase generator.

18. A method for reducing delay mismatch owing to jitter, comprising:
receiving, from a phase generator, a signal and an inverted signal, wherein transitions of the signal and the inverted signal are misaligned based on respective delays affected by jitter; and
overriding the transitions of the signal and the inverted signal to eliminate the delay mismatch between the respective delays.

19. The method of claim 18 , wherein overriding the transitions of the signal and the inverted signal comprises applying a fixed delay to each of the signal and the inverted signal.

20. The method of claim 19 , further comprising:
receiving, at a gating stage, the signal, the inverted signal, and the fixed delay; and
applying, by the gating stage, the fixed delay to each of the signal and the inverted signal to override the transitions of the signal and the inverted signal.

Assignees

• Invensense Inc

Inventors

• Oliaei Omid
• Pellegrini Aurelio
• Ottini Daniele

Classifications

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03M3/348

  using return-to-zero signals · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03K5/1515

  non-overlapping · CPC title