Methods of forming microelectronic device assemblies and packages

Patent metadata

Field	Value
Publication number	US-12199068-B2
Application number	US-202217817690-A
Country	US
Kind code	B2
Filing date	Aug 5, 2022
Priority date	Oct 17, 2019
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.

First claim

What is claimed is:

1. A method, comprising:
fabricating active circuitry on die locations of an active surface of a semiconductor substrate;
testing to determine known good die (KGD) locations;
singulating the semiconductor substrate into individual KGD;
operably coupling each KGD with conductive traces on a dielectric material; and
forming stacks of the individual KGD as stacks of singulated semiconductor dice, the conductive traces extending over active surfaces thereof and beyond at least one lateral periphery thereof on the dielectric material;
forming stacks of the singulated semiconductor dice in mutually spaced relationship on a substrate;
forming via holes through the conductive traces and the dielectric material at locations extending beyond the at least one lateral periphery of the semiconductor dice of the stacks to conductive pads or traces on an adjacent surface of the substrate; and
filling the via holes with a conductive material.

2. A method, comprising:
providing singulated semiconductor dice with conductive traces extending over active surfaces thereof and beyond at least one lateral periphery thereof on a dielectric material;
forming stacks of the singulated semiconductor dice in mutually spaced relationship on a substrate;
forming via holes through the conductive traces and the dielectric material at locations extending beyond the at least one lateral periphery of the semiconductor dice of the stacks to conductive pads or traces on an adjacent surface of the substrate;
filling the via holes with a conductive material; and
after filling the via holes with the conductive material:
encapsulating the stacks of semiconductor dice on the substrate with an epoxy molding compound (EMC);
applying or forming conductive elements on the substrate opposite the stacks of semiconductor dice;
testing the stacks of semiconductor dice; and
singulating the stacks of semiconductor dice through the EMC and the substrate.

3. The method of claim 2 , wherein encapsulating the stacks of semiconductor dice comprises leaving tops of the stacks exposed and applying a thermal interface material (TIM) and heat sink to the top of each stack.

4. The method of claim 1 , wherein the singulated semiconductor dice comprise DRAM, NAND Flash or 3D XPoint (SXP) memory dice.

5. A method, comprising:
laminating a polymer film over active surfaces of mutually spaced semiconductor dice;
forming openings through the polymer film to expose bond pads of the semiconductor dice;
forming conductive traces extending from exposed bond pads at least to predetermined via locations; and
singulating the semiconductor dice and polymer film laterally outward of the predetermined via locations;
forming stacks of the singulated semiconductor dice in mutually spaced relationship on a substrate;
forming via holes through the conductive traces and the dielectric material at locations extending beyond the at least one lateral periphery of the semiconductor dice of the stacks to conductive pads or traces on an adjacent surface of the substrate; and
filling the via holes with a conductive material.

6. The method of claim 5 , further comprising, before laminating the polymer film over the mutually spaced semiconductor dice, placing singulated semiconductor dice by back sides thereof in the mutually spaced relationship on an adhesive film.

7. The method of claim 6 , wherein placing singulated semiconductor dice by the back sides thereof in the mutually spaced relationship on an adhesive film comprises placing the semiconductor dice on a die attach film (DAF) or a film over die (FOD) material.

8. The method of claim 5 , wherein laminating a polymer film comprises laminating a non-conductive film (NCF), a b-staged polyimide film, a polytetrafluoroethylene (PTFE) film.

Assignees

• Micron Technology Inc

Inventors

• Fay Owen R
• Richards Randon K
• Limaye Aparna U
• Lim Dong Soon
• Yoo Chan H
• Street Bret K
• Nakano Eiichi
• Luo Shijian

Classifications

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title

• H10W90/722

  between stacked chips · CPC title