Heterogeneous nested interposer package for IC chips

Patent metadata

Field	Value
Publication number	US-12199048-B2
Application number	US-202318397915-A
Country	US
Kind code	B2
Filing date	Dec 27, 2023
Priority date	Jun 11, 2019
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

First claim

What is claimed is:

1. An electronics package, comprising:
an interposer comprising silicon, the interposer comprising vias that provide connections between pads on a bottom of the interposer and a redistribution layer on a top of the interposer;
a first die over the interposer, the first die coupled to the redistribution layer of the interposer by first interconnects;
a second die over the interposer and laterally spaced apart from the first die, the second die coupled to the redistribution layer of the interposer by second interconnects;
a first mold layer between the first die and the interposer and between the second die and the interposer, the first mold layer laterally between and in contact with the first die and the second die, and the first mold layer in contact with the first interconnects and with the second interconnects;
bumps on the pads on the bottom of the interposer and vertically beneath the vias of the interposer, the bumps vertically beneath the first die and vertically beneath the second die; and
a second mold layer beneath the interposer and in contact with a side of the interposer, the second mold layer in contact with the bumps and with the pads on the bottom of the interposer.

2. The electronics package of claim 1 , wherein the first mold layer has an uppermost surface at a same level as an uppermost surface of the first die.

3. The electronics package of claim 2 , wherein the uppermost surface of the first mold layer is at a same level as an uppermost surface of the second die.

4. The electronics package of claim 1 , wherein the second mold layer is in contact with a second side of the interposer, the second side laterally opposite the side.

5. The electronics package of claim 4 , wherein the second mold layer is in contact with less than an entirety of the side of the interposer, and with less than an entirety of the second side of the interposer.

6. The electronics package of claim 1 , wherein the second mold layer has an edge in vertical alignment with an edge of the first mold layer.

7. The electronics package of claim 1 , further comprising:
an underfill material between the interposer and the first mold layer.

8. A method of fabricating an electronics package, the method comprising:
coupling a first die to a redistribution layer of an interposer with first interconnects, the interposer comprising vias that provide connections between pads on a bottom of the interposer and the redistribution layer on a top of the interposer;
coupling a second die to the redistribution layer of the interposer with second interconnects;
forming a first mold layer between the first die and the interposer and between the second die and the interposer, the first mold layer laterally between and in contact with the first die and the second die, and the first mold layer in contact with the first interconnects and with the second interconnects;
forming bumps on the pads on the bottom of the interposer and vertically beneath the vias of the interposer, the bumps vertically beneath the first die and vertically beneath the second die; and
forming a second mold layer beneath the interposer and in contact with a side of the interposer, the second mold layer in contact with the bumps and with the pads on the bottom of the interposer.

9. The method of claim 8 , wherein the first mold layer has an uppermost surface at a same level as an uppermost surface of the first die.

10. The method of claim 9 , wherein the uppermost surface of the first mold layer is at a same level as an uppermost surface of the second die.

11. The method of claim 8 , wherein the second mold layer is in contact with a second side of the interposer, the second side laterally opposite the side.

12. The method of claim 11 , wherein the second mold layer is in contact with less than an entirety of the side of the interposer, and with less than an entirety of the second side of the interposer.

13. The method of claim 8 , wherein the second mold layer has an edge in vertical alignment with an edge of the first mold layer.

14. The method of claim 8 , further comprising:
forming an underfill material between the interposer and the first mold layer.

15. An electronic system, comprising:
a board;
a package substrate coupled to the board; and
an electronics package coupled to the package substrate, the electronics package comprising:
an interposer comprising silicon, the interposer comprising vias that provide connections between pads on a bottom of the interposer and a redistribution layer on a top of the interposer;
a first die over the interposer, the first die coupled to the redistribution layer of the interposer by first interconnects;
a second die over the interposer and laterally spaced apart from the first die, the second die coupled to the redistribution layer of the interposer by second interconnects;
a first mold layer between the first die and the interposer and between the second die and the interposer, the first mold layer laterally between and in contact with the first die and the second die, and the first mold layer in contact with the first interconnects and with the second interconnects;
bumps on the pads on the bottom of the interposer and vertically beneath the vias of the interposer, the bumps vertically beneath the first die and vertically beneath the second die; and
a second mold layer beneath the interposer and in contact with a side of the interposer, the second mold layer in contact with the bumps and with the pads on the bottom of the interposer.

16. The electronic system of claim 15 , further comprising:
a battery coupled to the board.

17. The electronic system of claim 15 , further comprising:
a camera coupled to the board.

18. The electronic system of claim 15 , further comprising:
a display coupled to the board.

19. The electronic system of claim 15 , further comprising:
a global positioning system (GPS) coupled to the board.

20. The electronic system of claim 15 , further comprising:
a communication chip coupled to the board.

Assignees

• Intel Corp

Inventors

• Mallik Debendra
• Mahajan Ravindranath
• Sankman Robert
• Liff Shawna
• Pietambaram Srinivas
• Penmecha Bharat

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/0198 Primary

  batch processes · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title